LTC3601
16
3601fc
For more information www.linear.com/LTC3601
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I
2
R loss:
I
2
R LOSS” = I
OUT
2
· (R
SW
+ R
L
)
2. The internal LDO supplies the power to the INTV
CC
rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the DC
control bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges
of the internal top and bottom power MOSFETs and f
is the switching frequency. For estimation purposes,
(Q
T
+ Q
B
) on the LTC3601 is approximately 1nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent cur-
rent and multiply by V
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) • V
IN
3. Other “hidden” losses such as transition loss, cop-
per trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends in
the saturated region during switch node transitions. The
LTC3601 internal power devices switch quickly enough
that these losses are not significant compared to other
sources.
Other losses, including diode conduction losses during
dead time and inductor core losses, generally account
for less than 2% total additional loss.
APPLICATIONS INFORMATION
Thermal Considerations
The LTC3601 requires the exposed package backplane
metal (PGND pin on the QFN, SGND pin on the MSOP
package) to be well soldered to the PC board to provide
good thermal contact. This gives the QFN and MSOP
packages exceptional thermal properties, compared to
other packages of similar size, making it difficult in normal
operation to exceed the maximum junction temperature
of the part. In many applications, the LTC3601 does not
dissipate much heat due to its high efficiency and low
thermal resistance package backplane. However, in applica-
tions in which the LTC3601 is running at a high ambient
temperature, high input voltage, high switching frequency,
and maximum output current, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off until temperature
decreases approximately 10°C.
Thermal analysis should always be performed by the user
to ensure the LTC3601 does not exceed the maximum
junction temperature.
The temperature rise is given by:
T
RISE
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
Consider the example in which an LTC3601EUD is operat-
ing with I
OUT
= 1.5A, V
IN
= 12V, f = 4MHz, V
OUT
= 1.8V,
and an ambient temperature of 70°C. From the Typical
Performance Characteristics section the R
DS(ON)
of the top
switch is found to be nominally 130mΩ while that of the
bottom switch is nominally 100mΩ yielding an equivalent
power MOSFET resistance R
SW
of:
R
DS(ON)
TOP • 1.8/12 + R
DS(ON)
BOT • 10.2/12 = 105mΩ.
LTC3601
17
3601fc
For more information www.linear.com/LTC3601
From the previous section, I
GATECHG
is ~4mA when f =
4MHz, and the spec table lists the typical I
Q
to be 1mA.
Therefore, the total power dissipation due to resistive
losses and LDO losses is:
P
D
= I
OUT
2
• R
SW
+ V
IN
• (I
GATECHG +
I
Q
)
P
D
= (1.5)
2
• (0.105) + 12V • 5mA = 296mW
The QFN 3mm × 3mm package junction-to-ambient thermal
resistance, θ
JA
, is around 45°C/W. Therefore, the junction
temperature of the regulator operating in a 70°C ambient
temperature is approximately:
T
J
= 0.296 • 45 + 70 = 83.3°C
which is well below the specified maximum junction
temperature of 125°C.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3601.
1. Do the capacitors C
IN
connect to V
IN
and PGND as close
to the pins as possible? These capacitors provide the AC
current to the internal power MOSFETs and drivers. The
(–) plate of C
IN
should be closely connected to PGND
and the (–) plate of C
OUT
.
2. The output capacitor, C
OUT
, and inductor L1 should
be closely connected to minimize loss. The (–) plate
of C
OUT
should be closely connected to PGND and the
(–) plate of C
IN
.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line termi-
nated near SGND. The feedback signal, V
FB
, should be
routed away from noisy components and traces such as
the SW line, and its trace length should be minimized.
In addition, RT and the loop compensation components
should be terminated to SGND.
4. Keep sensitive components away from the SW pin. The
R
RT
resistor, the feedback resistors, the compensation
components, and the INTV
CC
bypass capacitor should
all be routed away from the SW trace and the inductor.
5. A ground plane is preferred, but if not available the
signal and power grounds should be segregated with
both connecting to a common, low noise reference
point. The point at which the ground terminals of the
V
IN
and V
OUT
bypass capacitors are connected makes a
good, low noise reference point. The connection to the
PGND pin should be made with a minimal resistance
trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside connection of the IC.
APPLICATIONS INFORMATION
LTC3601
18
3601fc
For more information www.linear.com/LTC3601
APPLICATIONS INFORMATION
16 15 14 13
5 6 7 8
17
9
10
11
12
4
3
2
1
R2
VIA TO
V
OUT
VIA TO
PGND
R1
C
FWD
VIAS TO
INTV
CC
VIAS TO
PGND
C
IN
C
OUT
L1
SW
C
BOOST
VIAS
TO PGND
C
INTVCC
PGND
VIAS TO
GROUND
PLANE
VIAS TO
GROUND
PLANE
VIA TO R2
V
IN
V
OUT
3601 F05
Figure 5. QFN Layout Example

LTC3601IUD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5A, 15V, 4MHz Monolithic Synchronous Step-Down Regulator in 3x3 QFN
Lifecycle:
New from this manufacturer.
Delivery:
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