DAC8408
–9–
REV. A
Figure 4. Equivalent DAC Circuit (AII Digital Inputs LOW)
DIGITAL SECTION
Figure 5 shows the digital input/output structure for one bit.
The digital WR,
WR, and RD controls shown in the figure are
internally generated from the external A/
B, R/W, DS1, and DS2
signals. The combination of these signals decide which DAC is
selected. The digital inputs are CMOS inverters, designed such
that TTL input levels (2.4 V and 0.8 V) are converted into
CMOS logic levels. When the digital input is in the region of 1.2 V
to 1.8 V, the input stages operate in their linear region and draw
current from the +5 V supply (see Typical Supply Current vs.
Logic Level curve on page 6). It is recommended that the digital
input voltages be as close to V
DD
and DGND as is practical in
order to minimize supply currents. This allows maximum sav-
ings in power dissipation inherent with CMOS devices. The
three-state readback digital output drivers (in the active mode)
provide TTL-compatible digital outputs with a fan-out of one
TTL load. The three state digital readback leakage-current is
typically 5 nA.
Figure 5. Digital Input/Output Structure
INTERFACE LOGIC SECTION
DAC Operating Modes
• All DACs in HOLD MODE.
• DAC A, B, C, or D individually selected (WRITE MODE).
• DAC A, B, C, or D individually selected (READ MODE).
• DACs A and C simultaneously selected (WRITE MODE).
• DACs B and D simultaneously selected (WRITE MODE).
DAC Selection: Control inputs,
DS1, DS2, and A/B select
which DAC can accept data from the input port (see Mode Se-
lection Table).
Mode Selection: Control inputs
DS and R/W control the oper-
ating mode of the selected DAC.
Write Mode: When the control inputs
DS and R/W are both
low, the selected DAC is in the write mode. The input data
latches of the selected DAC are transparent, and its analog out-
put responds to activity on the data inputs DB0–DB7.
Hold Mode: The selected DAC latch retains the data that was
present on the bus line just prior to
DS or R/W going to a high
state. All analog outputs remain at the values corresponding to
the data in their respective latches.
Read Mode: When
DS is low and R/W is high, the selected
DAC is in the read mode, and the data held in the appropriate
latch is put back onto the data bus.
MODE SELECTION TABLE
Control Logic
DS1 DS2 A/B R/W Mode DAC
L H H L WRITE A
L H L L WRITE B
H L H L WRITE C
H L L L WRITE D
L H H H READ A
L H L H READ B
H L H H READ C
H L L H READ D
L L H L WRITE A&C
L L L L WRITE B&D
H H X X HOLD A/B/C/D
L L H H HOLD A/B/C/D
L L L H HOLD A/B/C/D
L = Low State, H = High State, X = Irrelevant
DAC8408
–10–
REV. A
BASIC APPLICATIONS
Some basic circuit configurations are shown in Figures 6 and 7.
Figure 6 shows the DAC8408 connected in a unipolar configu-
ration (2-Quadrant Multiplication), and Table I shows the Code
Table. Resistors R1, R2, R3, and R4 are used to trim full scale
output. Full-scale output voltage = V
REF
–1 LSB = V
REF
(1–2
–8
)
or V
REF
× (255/256) with all digital inputs high. Low tempera-
ture coefficient (approximately 50 ppm/°C) resistors or trim-
mers should be selected if used. Full scale can also be adjusted
using V
REF
voltage. This will eliminate resistors R1, R2, R3, and
R4. In many applications, R1 through R4 are not required, and
the maximum gain error will then be that of the DAC.
Each DAC exhibits a variable output resistance that is code-
dependent. This produces a code-dependent, differential non-
linearity term at the amplifier’s output which can have a maxi-
mum value of 0.67 × the amplifier’s offset voltage. This differ-
ential nonlinearity term adds to the R-2R resistor ladder differ-
ential-nonlinearity; the output may no longer be monotonic. To
maintain monotonicity and minimize gain and linearity errors, it
is recommended that the op amp offset voltage be adjusted to
less than 10% of 1 LSB (1 LSB = 2
–8
× V
REF
or 1/256 × V
REF
),
or less than 3.9 mV over the operating temperature range. Zero-
scale output voltage (with all digital inputs low) may be adjusted
using the op amp offset adjustment. Capacitors C1, C2, C3,
and C4 provide phase compensation and help prevent overshoot
and ringing when using high speed op amps.
Figure 7 shows the recommended circuit configuration for the
bipolar operation (4-quadrant multiplication), and Table II shows
the Code Table. Trimmer resistors R17, R18, R19, and R20
are used only if gain error adjustments are required and range
between 50 and 1000 . Resistors R21, R22, R23, and R24
will range betwen 50 and 500 . If these resistors are used, it
is essential that resistor pairs R9–R13, R10–R14, R11–R15,
R12–R16 are matched both in value and tempco. They should
be within 0.01%; wire wound or metal foil types are preferred
for best temperature coefficient matching. The circuits of Figure
6 and 7 can either be used as a fixed reference D/A converter, or
as an attenuator with an ac input voltage.
Table I. Unipolar Binary Code Table (Refer to Figure 6)
DAC Data Input
MSB LSB Analog Output
1 1 1 1 1 1 1 1 –V
REF
255
256
1 0 0 0 0 0 0 1 –V
REF
129
256
1 0 0 0 0 0 0 0 –V
REF
128
256
=
VIN
2
0 1 1 1 1 1 1 1 –V
REF
127
256
0 0 0 0 0 0 0 1 –V
REF
1
256
0 0 0 0 0 0 0 0 –V
REF
0
256
= 0
NOTE
1 LSB = (2
–8
) (V
REF
) =
1
256
(V
REF
)
Figure 6. Quad DAC Unipolar Operation (2-Quadrant Multiplication)
DAC8408
–11–
REV. A
Figure 7. Quad DAC Bipolar Operation (4-Quadrant Multiplication)
Table II. Bipolar (Offset Binary) Code Table
(Refer to Figure 7)
DAC Data Input Analog Output
MSB LSB (DAC A OR DAC B)
1 1 1 1 1 1 1 1 +V
REF
127
128
1 0 0 0 0 0 0 1 +V
REF
1
128
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 –V
REF
1
128
0 0 0 0 0 0 0 1 –V
REF
127
128
0 0 0 0 0 0 0 0 –V
REF
128
128
NOTE
1 LSB = (2
–7
) (V
REF
) =
1
128
(V
REF
)
APPLICATION HINTS
General Ground Management: AC or transient voltages be-
tween AGND and DGND can appear as noise at the DAC8408’s
analog output. Note that in Figures 5 and 6, I
OUT2A
/I
OUT2B
and
I
OUT 2C
/I
OUT 2D
are connected to AGND. Therefore, it is rec-
ommended that AGND and DGND be tied together at the
DAC8408 socket. In systems where AGND and DGND are tied
together on the backplane, two diodes (1N914 or equivalent)
should be connected in inverse parallel between AGND and
DGND.
Write Enable Timing: During the period when both
DS and
R/
W are held low, the DAC latches are transparent and the ana-
log output responds directly to the digital data input. To pre-
vent unwanted variations of the analog output, the R/
W should
not go low until the data bus is fully settled (DATA VALID).

DAC8408FPC

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
IC DAC 8BIT QUAD W/MEMORY 28PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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