Philips Semiconductors Product data sheet
PCA9513; PCA9514Hot swappable I
2
C and SMBus bus buffer
2004 Oct 05
7
Propagation Delays
The delay for a rising edge is determined by the combined pull-up
current from the bus resistors and the rise time accelerator current
source and the effective capacitance on the lines. If the pull-up
currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides.
The t
PLH
may be negative if the output capacitance is less than the
input capacitance and would be positive if the output capacitance is
larger than the input capacitance, when the currents are the same.
The t
PHL
can never be negative because the output does not start to
fall until the input is below 0.7V
CC
, and the output turn on has a non
zero delay, and the output has a limited maximum slew rate, and
even if the input slew rate is slow enough that the output catches up
it will still lag the falling voltage of the input by the offset voltage. The
maximum t
PHL
occurs when the input is driven LOW with zero delay
and the output is still limited by its turn on delay and the falling edge
slew rate. The output falling edge slew rate is a function of the
internal maximum slew rate which is a function of temperature, V
CC
,
and process, as well as the load current and the load capacitance.
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on
to quickly slew the SDA and SCL lines HIGH once the input level of
0.8 V for the PCA9513 and PCA9514 are exceeded. The rising edge
rate should be at least 1.25 V/µs to guarantee turn on of the
accelerators. The 0.8 V threshold of PCA9513 and PCA9514 allows
for larger bounce-or-noise without falsely triggering the rise time
accelerators.
READY Digital Output
This pin provides a digital flag which is LOW when either ENABLE is
LOW or the start-up sequence described earlier in this section has
not been completed. READY goes HIGH when ENABLE is HIGH
and start-up is complete. The pin is driven by an open drain
pull-down capable of sinking 3 mA while holding 0.4 V on the pin.
Connect a resistor of 10 kΩ to V
CC
to provide the pull-up.
ENABLE Low Current Disable
Grounding the ENABLE pin disconnects the backplane side from the
card side, disables the rise-time accelerators, drives READY LOW,
disables the bus precharge circuitry, and puts the part in a LOW
current state. When the pin voltage is driven all the way to V
CC
, the
part waits for data transactions on both the backplane and card
sides to be complete before reconnecting the two sides.
Resistor Pull-up Value Selection
The system pull-up resistors must be strong enough to provide a
positive slew rate of 1.25 V/µs on the SDA and SCL pins, in order to
activate the boost pull-up currents during rising edges. Choose
maximum resistor value using the formula:
v @
*
where R is the pull-up resistor value in Ω, V
CC(MIN)
is the
minimum V
CC
voltage in volts and C is the equivalent bus
capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always choose R ≤
16 kΩ for V
CC
= 5.5 V maximum, R ≤ 24 kΩ for V
CC
= 3.6 V
maximum. The start-up circuitry requires logic high voltages on
SDAOUT and SCLOUT to connect the backplane to the card, and
these pull-up values are needed to overcome the precharge voltage
(PCA9511 only). See the curves in Figures 7 and 8 for guidance in
resistor pull-up selection.
30
20
15
21
5
0
0 100 200 300 400
C
BUS
(pF)
R
PULLUP
(kΩ)
25
RECOMMENDED
PULL-UP
R
MAX
= 24 kΩ
RISE-TIME > 300 ns
SW02115
Figure 7. Bus requirements for 3.3 V systems
20
15
21
5
0
0 100 200 300 400
C
BUS
(pF)
R
PULLUP
(kΩ)
RECOMMENDED
PULL-UP
R
MAX
= 16 kΩ
RISE-TIME
> 300 ns
SW02116
Figure 8. Bus requirements for 5 V systems
Minimum SDA and SCL Capacitance Requirements
The device connection circuitry requires a minimum capacitance
loading on the SDA and SCL pins in order to function properly. The
value of this capacitance is a function of V
CC
and the bus pull-up
resistance. Estimate the bus capacitance on both the backplane and
the card data and clock buses, and refer to Figures 7 and 8 to
choose appropriate pull-up resistor values. Note from the figures
that 5 V systems should have at least 47 pF capacitance on their
buses and 3.3 V systems should have at least 22 pF capacitance for
proper operation. Although the device has been designed to be
marginally stable with smaller capacitance loads, for applications
with less capacitance, provisions need to be made to add a
capacitor to ground to ensure these minimum capacitance
conditions if oscillations are noticed during initial signal integrity
verification.
