LTC3537
9
3537fd
PIN FUNCTIONS
MODE (Pin 1): Logic Controlled Input for the Auto-Burst
Mode Feature.
MODE = High: PWM operation with Burst Mode
Operation
MODE = Low: PWM operation only
LBI (Pin 2): Low-Battery Comparator Non-Inverting Input.
(Comparator enabled with ENBST or ENLDO)
SGND (Pin 3): Signal Ground. Provide a short direct PCB
path between GND and the (–) side of the input and output
capacitors.
V
INB
(Pin 4): Input Supply for the Step-Up Converter.
Connect a minimum of 1µF ceramic decoupling capacitor
from this pin to ground.
PGDB (Pin 5): Power Good Indicator for the Boost Con-
verter. This is an open-drain output that sinks current
when V
OUTB
is less than 94% of the programmed voltage.
ENBST (Pin 6): Logic controlled shutdown input for the
boost converter.
ENBST = High: Normal operation
ENBST = Low: Shutdown
PGDL (Pin 7): Power Good Indicator for the LDO Regula-
tor. This is an open-drain output that sinks current when
V
OLDO
is less than 96% of the programmed voltage.
ENLDO (Pin 8): Logic Controlled Shutdown Input for the
LDO Regulator.
ENLDO = High: Normal operation
ENLDO = Low: Shutdown
FBB (Pin 9): Feedback Input to the g
m
Error Amplifi er
of the Boost Converter. Connect resistor divider tap to
this pin. The output voltage can be adjusted from 1.5V
to 5.25V by:
V
OUTB
= 1.21V • [1 + (R2/R1)]
FBL (Pin 10): Feedback Input to the g
m
Error Amplifi er of
the LDO. Connect resistor divider tap to this pin. The output
voltage can be adjusted from 0.6V (typical) to 5V by:
V
OLDO
= 0.6V • [1 + (R4/R3)]
V
OLDO
(Pin 11): LDO Regulator Output. PCB trace from
V
OLDO
to the output fi lter capacitor (1µF minimum) should
be as short and as wide as possible.
V
INL
(Pin 12): Input Supply for the LDO Regulator.
V
OUTB
(Pin 13): Output Voltage Sense Input and Drain
of the Internal Synchronous Rectifi er. PCB trace length
from V
OUTB
to the output fi lter capacitor (4.7µF minimum)
should be as short and wide as possible.
SW (Pin 14): Switch Pin. Connect the inductor between
SW and V
INB
. Keep these PCB trace lengths as short and
wide as possible to reduce EMI. If the inductor current falls
to zero or ENBST is low, an internal anti-ringing switch is
connected from SW to V
INB
to minimize EMI.
PGND (Pin 15): Power Ground. Provide a short direct
PCB path between GND and the (–) side of the input and
output capacitors.
LBO (Pin 16): Low-Battery Comparator Output. (Open-
Drain)
GND (Exposed Pad Pin 17): Power Ground. The Exposed
Pad must be soldered to the PCB.
