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74HC595DB-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 28 February 2017
10 / 23
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ
[1]
Max Min Max Min Max
Unit
OE to Qn; see Figure 13
[4]
V
CC
= 2 V - 41 150 - 190 - 225 ns
V
CC
= 4.5 V - 15 30 - 38 - 45 ns
t
dis
disable time
V
CC
= 6 V - 12 27 - 33 - 38 ns
SHCP HIGH or LOW;
see Figure 9
V
CC
= 2 V 75 17 - 95 - 110 - ns
V
CC
= 4.5 V 15 6 - 19 - 22 - ns
V
CC
= 6 V 13 5 - 16 - 19 - ns
STCP HIGH or LOW;
see Figure 10
V
CC
= 2 V 75 11 - 95 - 110 - ns
V
CC
= 4.5 V 15 4 - 19 - 22 - ns
V
CC
= 6 V 13 3 - 16 - 19 - ns
MR LOW; see Figure 12
V
CC
= 2 V 75 17 - 95 - 110 - ns
V
CC
= 4.5 V 15 6 - 19 - 22 - ns
t
W
pulse width
V
CC
= 6 V 13 5 - 16 - 19 - ns
DS to SHCP; see Figure 11
V
CC
= 2 V 50 11 - 65 - 75 - ns
V
CC
= 4.5 V 10 4 - 13 - 15 - ns
V
CC
= 6 V 9 3 - 11 - 13 - ns
SHCP to STCP;
see Figure 11
V
CC
= 2 V 75 22 - 95 - 110 - ns
V
CC
= 4.5 V 15 8 - 19 - 22 - ns
t
su
set-up time
V
CC
= 6 V 13 7 - 16 - 19 - ns
DS to SHCP; see Figure 11
V
CC
= 2 V 3 -6 - 3 - 3 - ns
V
CC
= 4.5 V 3 -2 - 3 - 3 - ns
t
h
hold time
V
CC
= 6 V 3 -2 - 3 - 3 - ns
MR to SHCP; see Figure 12
V
CC
= 2 V 50 -19 - 65 - 75 - ns
V
CC
= 4.5 V 10 -7 - 13 - 15 - ns
t
rec
recovery
time
V
CC
= 6 V 9 -6 - 11 - 13 - ns
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 28 February 2017
11 / 23
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ
[1]
Max Min Max Min Max
Unit
SHCP or STCP; see Figure 9
and Figure 10
V
CC
= 2 V 9 30 - 4.8 - 4 - MHz
V
CC
= 4.5 V 30 91 - 24 - 20 - MHz
f
max
maximum
frequency
V
CC
= 6 V 35 108 - 28 - 24 - MHz
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
= GND to V
CC
[5]
[6]
- 115 - - - - - pF
74HCT595-Q100; V
CC
= 4.5 V to 5.5 V
SHCP to Q7S; see Figure 9
[2]
- 25 42 - 53 - 63 nst
pd
propagation
delay
STCP to Qn; see Figure 10
[2]
- 24 40 - 50 - 60 ns
t
PHL
HIGH
to LOW
propagation
delay
MR to Q7S; see Figure 12 - 23 40 - 50 - 60 ns
t
en
enable time OE to Qn; see Figure 13
[3]
- 21 35 - 44 - 53 ns
t
dis
disable time OE to Qn; see Figure 13
[4]
- 18 30 - 38 - 45 ns
SHCP HIGH or LOW;
see Figure 9
16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure 10
16 5 - 20 - 24 - ns
t
W
pulse width
MR LOW; see Figure 12 20 8 - 25 - 30 - ns
DS to SHCP; see Figure 10 16 5 - 20 - 24 - nst
su
set-up time
SHCP to STCP;
see Figure 10
16 8 - 20 - 24 - ns
t
h
hold time DS to SHCP; see Figure 11 3 -2 - 3 - 3 - ns
t
rec
recovery
time
MR to SHCP; see Figure 12 10 -7 - 13 - 15 - ns
f
max
maximum
frequency
SHCP and STCP;
see Figure 9 and Figure 10
30 52 - 24 - 20 - MHz
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
= GND to V
CC
- 1.5 V
[5]
[6]
- 130 - - - - - pF
[1] Typical values are measured at nominal supply voltage.
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] t
en
is the same as t
PZL
and t
PZH
.
[4] t
dis
is the same as t
PLZ
and t
PHZ
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in μW).
P
D
= C
PD
× V
CC
2
× f
i
+ Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
Σ(C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 28 February 2017
12 / 23
V
CC
= supply voltage in V.
[6] All 9 outputs switching.
11.1 Waveforms and test circuit
mna557
SHCP input
Q7S output
t
PLH
t
PHL
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 9. Shift clock pulse, maximum frequency and input to output propagation delays
mna558
STCP input
Qn output
t
PLH
t
PHL
t
W
t
su
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M
SHCP input
V
I
GND
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Figure 10. Storage clock to output propagation delays
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

74HC595DB-Q100J

Mfr. #:
Buy 74HC595DB-Q100J
Manufacturer:
Nexperia
Description:
Counter Shift Registers 8bit serial-in srial or parallel-out
Lifecycle:
New from this manufacturer.
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