Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 28 February 2017
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6.2 Pin description
Table 2. Pin description
Symbol Pin Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable input (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
V
CC
16 supply voltage
7 Functional description
Table 3. Function table
[1]
Control Input Output
SHCP STCP OE MR DS Q7S Qn
Function
X X L L X L NC a LOW-level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
↑ X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑ ↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
