IDT1338
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC
IDT®
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 13
IDT1338 REV S 111214
AC Electrical Characteristics
(V
CC
= V
CC(MIN)
to V
CC(MAX)
, TA = -40°C to +85°C) (Note 1)
WARNING: Negative undershoots below -0.3 V while the device is in battery-backed mode may cause loss
of data.
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: All voltages referenced to ground.
Note 3: SCL only.
Note 4: SDA and SQW/OUT.
Note 5: I
CCA
—SCL clocking at max frequency = 400 kHz.
Note 6: Specified with the I
2
C bus inactive.
Parameter Symbol Conditions Min. Typ. Max. Units
SCL Clock Frequency f
SCL
Fast Mode 100 400 kHz
Standard Mode 0 100
Bus Free Time Between a STOP and
START Condition
t
BUF
Fast Mode 1.3 µs
Standard Mode 4.7
Hold Time (Repeated) START
Condition, Note 8
t
HD:STA
Fast Mode 0.6 µs
Standard Mode 4.0
Low Period of SCL Clock t
LOW
Fast Mode 1.3 µs
Standard Mode 4.7
High Period of SCL Clock t
HIGH
Fast Mode 0.6 µs
Standard Mode 4.0
Setup Time for a Repeated START
Condition
t
SU:STA
Fast Mode 0.6 µs
Standard Mode 4.7
Data Hold Time (Notes 9, 10) t
HD:DAT
Fast Mode 0 0.9 µs
Standard Mode 0
Data Setup Time (Note 11) t
SU:DAT
Fast Mode 100 ns
Standard Mode 250
Rise Time of Both SDA and SCL
Signals (Note 12)
t
R
Fast Mode 20 + 0.1C
B
300 ns
Standard Mode 20 + 0.1C
B
1000
Fall Time of Both SDA and SCL Signals
(Note 12)
t
F
Fast Mode 20 + 0.1C
B
300 ns
Standard Mode 20 + 0.1C
B
300
Setup Time for STOP Condition t
SU:STO
Fast Mode 0.6 µs
Standard Mode 4.0
Capacitive Load for Each Bus Line
(Note 12)
C
B
400 pF
I/O Capacitance (SDA, SCL) C
I/O
Note 13 10 pF
Oscillator Stop Flag (OSF) Delay t
OSF
Note 14 100 ms
IDT1338
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC
IDT®
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 14
IDT1338 REV S 111214
Note 7: Measured with a 32.768 kHz crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHMIN
of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+
t
SU:DAT
= 1000 + 250 = 1250 ns before the SCL line is released.
Note 12: C
B
—total capacitance of one bus line in pF.
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the
voltage range of 0.0V <
V
CC
< V
CC
MAX and 1.3 V < V
BACKUP
< 3.7 V.
Timing Diagram
IDT1338
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC
IDT®
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 15
IDT1338 REV S 111214
Typical Operating Characteristics
IBAT vs VBAT
(IDT1338-31)
494
534
574
614
654
694
734
1.3 1.8 2.3 2.8 3.3
VBat (V)
Supply current (nA)
SQWE=1
SQWE=0
Icc vs Vcc
(IDT1338-31)
0
5
10
15
20
25
2.73.23.74.24.75.2
Vcc (V)
Supply Current (uA)
SCL=400kHz
SCL=0Hz
IBAT vs Temperature
400
500
600
700
800
-40-20020406080
Temperature (C)
IBAT (nA)
SQWE=1
SQWE=0
Oscillator Frequency vs Supply Voltage
32767.750000
32767.800000
32767.850000
32767.900000
32767.950000
2.7 3.2 3.7 4.2 4.7 5.2
Oscillator Supply Voltage (V)
Frequency (Hz)
Freq

1338AC-18SRGI8

Mfr. #:
Manufacturer:
IDT
Description:
Real Time Clock RTC w/Battery Backed Non-Volatile RAM
Lifecycle:
New from this manufacturer.
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