1338AC-18SRGI8 Datasheet 1338-31DVGI8, 1338-31DCGI8, 1338-18DCGI | P4-P6

IDT1338

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC

IDT®

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 4

IDT1338 REV S 111214

ESR (Effective Series Resistance)

Choose the crystal with lower ESR. A low ESR helps the

crystal to start up and stabilize to the correct output

frequency faster compared to high ESR crystals.

Frequency Tolerance

The frequency tolerance for 32 KHz crystals should be

specified at nominal temperature (+25°C) on the crystal

manufacturer datasheet. The crystals used with IDT1338

typically have a frequency tolerance of +/-20ppm at +25°C.

Specifications for a typical 32kHz crystal used with our

device are shown in the table below.

PCB Design Consideration

• Signal traces between IDT device pins and the crystal

must be kept as short as possible. This minimizes

parasitic capacitance and sensitivity to crosstalk and

EMI. Note that the trace capacitances play a role in the

effective crystal load capacitance calculation.

• Data lines and frequently switching signal lines should be

routed as far away from the crystal connections as

possible. Crosstalk from these signals may disturb the

oscillator signal.

• Reduce the parasitic capacitance between X1 and X2

signals by routing them as far apart as possible.

• The oscillation loop current flows between the crystal and

the load capacitors. This signal path (crystal to CL1 to

CL2 to crystal) should be kept as short as possible and

ideally be symmetric. The ground connections for both

capacitors should be as close together as possible.

Never route the ground connection between the

capacitors all around the crystal, because this long

ground trace is sensitive to crosstalk and EMI.

• To reduce the radiation / coupling from oscillator circuit,

an isolated ground island on the GND layer could be

made. This ground island can be connected at one point

to the GND layer. This helps to keep noise generated by

the oscillator circuit locally on this separated island. The

ground connections for the load capacitors and the

oscillator should be connected to this island.

PCB Layout

PCB Assembly, Soldering and Cleaning

Board-assembly production process and assembly quality

can affect the performance of the 32 KHz oscillator.

Depending on the flux material used, the soldering process

can leave critical residues on the PCB surface. High

humidity and fast temperature cycles that cause humidity

condensation on the printed circuit board can create

process residuals. These process residuals cause the

insulation of the sensitive oscillator signal lines towards

each other and neighboring signals on the PCB to decrease.

High humidity can lead to moisture condensation on the

surface of the PCB and, together with process residuals,

reduce the surface resistivity of the board. Flux residuals on

the board can cause leakage current paths, especially in

humid environments. Thorough PCB cleaning is therefore

highly recommended in order to achieve maximum

performance by removing flux residuals from the board after

assembly. In general, reduction of losses in the oscillator

circuit leads to better safety margin and reliability.

Parameter Symbol Min Typ Max Units

Nominal Freq. f

32.768 kHz

Series Resistance ESR 110 k

Load Capacitance C

12.5 pF

IDT1338

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC

IDT®

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 5

IDT1338 REV S 111214

Power Control

A precise, temperature-compensated voltage reference and

a comparator circuit provides power-control function that

monitors the

level. The device is fully accessible and

data can be written and read when

is greater than V

However, when

falls below V

, the internal clock

registers are blocked from any access. If V

is less than

BAT

, the device power is switched from V

to V

BAT

when

drops below V

. If V

is greater than V

BAT

, the device

power is switched from

to V

BAT

when V

drops below

BAT

. The registers are maintained from the V

BAT

source

until

is returned to nominal levels (Table 1). After V

returns above V

, read and write access is allowed after

REC

(see the “Power-Up/Down Timing” diagram).

Table 1. Power Control

Power-up/down Timing

Table 2. Power-up/down Characteristics

Ambient Temperature -40 to +85C

Note 1 : This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay

occurs.

Note 2: Measured at typ VBAT level.

Supply Condition Read/Write

Access

Powered

< V

, V

< V

BAT

No V

BAT

< V

, V

> V

BAT

No V

> V

, V

< V

BAT

Ye s V

> V

, V

> V

BAT

Ye s V

Parameter Symbol Conditions Min. Typ. Max. Units

Recovery at Power-up t

REC

(see note 1) 2 ms

Fall Time; V

PF(MAX)

to V

PF(MIN)

VCCF

IDT1338-18, (see note 2) 3 ms

IDT1338-31, (see note 2) 3 ms

Rise Time; V

PF(MIN)

to V

PF(MAX)

VCCR

0µs

IDT1338

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM RTC

IDT®

REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 6

IDT1338 REV S 111214

RTC and RAM Address Map

The address map for the RTC and RAM registers shown in Table 3. The RTC registers and control register are located in

address locations 00H to 07H The RAM registers are located in address locations 08H to 3FH. During a multibyte access,

when the register pointer reaches 3FH (the end of RAM space) it wraps around to location 00H (the beginning of the clock

space). On an I

C START, STOP, or register pointer incrementing to location 00H, the current time and date is transferred to

a second set of registers. The time and date in the secondary registers are read in a multibyte data transfer, while the clock

continues to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.

Table 3. RTC and RAM Address Map

Note: Bits listed as “0” should always be written and read as 0.

Clock and Calendar

Table 3 shows the address map of the RTC registers. The

time and date information is obtained by reading the

appropriate register bytes. The time and calendar are set or

initialized by writing the appropriate register bytes. The

contents of the time and calendar registers are in the BCD

format. Bit 7 of Register 0 is the clock halt (CH) bit. When

this bit is set to 1, the oscillator is disabled. When cleared to

0, the oscillator is enabled. The clock can be halted

whenever the timekeeping functions are not required, which

decreases V

BAT

current.

The day-of-week register increments at midnight. Values

that correspond to the day of week are user-defined but

must be sequential (i.e., if 1 equals Sunday, then 2 equals

Monday, and so on). Illogical time and date entries result in

undefined operation.

When reading or writing the time and date registers,

secondary (user) buffers are used to prevent errors when

the internal registers update. When reading the time and

date registers, the user buffers are synchronized to the

internal registers on any start or stop, and when the address

pointer rolls over to zero. The countdown chain is reset

whenever the seconds register is written. Write transfers

occurs on the acknowledge pulse from the device. To avoid

rollover issues, once the countdown chain is reset, the

remaining time and date registers must be written within one

second. If enabled, the 1 Hz square-wave output transitions

high 500 ms after the seconds data transfer, provided the

oscillator is already running.

Note that the initial power-on state of all registers,

unless otherwise specified, is not defined. Therefore, it

is important to enable the oscillator (CH = 0) during

initial configuration.

The IDT1338 runs in either 12-hour or 24-hour mode. Bit 6

of the hours register is defined as the 12-hour or 24-hour

mode-select bit. When high, the 12-hour mode is selected.

In the 12-hour mode, bit 5 is the AM

/PM bit, with logic high

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Range

00H CH 10 seconds Seconds Seconds 00 - 59

01H 0 10 minutes Minutes Minutes 00 - 59

02H 0 12/24

AM/PM

10 hour Hour Hours

1 - 12

+ AM/PM

00 - 23

10 hour

03H00000 Day Day 1 - 7

04H 0 0 10 date Date Date 01 - 31

05H 0 0 0 10 month Month Month 01 - 12

06H 10 year Year Year 00 - 99

07H OUT 0 OSF SQWE 0 0 RS1 RS0 Control

08H -

3FH

RAM 56 x 8 00H - FFH

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

1338AC-18SRGI8

Mfr. #:

Buy 1338AC-18SRGI8

Manufacturer:

IDT

Description:

Real Time Clock RTC w/Battery Backed Non-Volatile RAM

Lifecycle:

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1338AC-18SRGI8

1338AC-18SRGI8

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