AD5313WBRUZ-REEL7 Datasheet AD5323ARUZ, AD5313ARUZ, AD5323BRUZ | P19-P21

AD5303/AD5313/AD5323

Rev. B | Page 19 of 28

POWER-DOWN MODES

The AD5303/AD5313/AD5323 have very low power consump-

tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW

with a 5 V supply. Power consumption can be further reduced

when the DACs are not in use by putting them into one of three

power-down modes, which are selected by Bit 13 and Bit 12

(PD1 and PD0) of the control word.

Table 7 shows how the

state of the bits corresponds to the mode of operation of that

particular DAC.

Table 7. PD1/PD0 Operating Modes

PD1 PD0 Operating Mode

0 0 Normal operation

0 1 Power-down (1 kΩ load to GND)

1 0 Power-down (100 kΩ load to GND)

1 1 Power-down (high impedance output)

When both bits are set to 0, the DACs work normally with their

normal power consumption of 300 μA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (50 nA at 3 V) when both DACs are powered down. Not

only does the supply current drop, but the output stage is also

internally switched from the output of the amplifier to a resistor

network of known values. This has the advantage that the

output impedance of the part is known while the part is in

power-down mode and provides a defined input condition

for whatever is connected to the output of the DAC amplifier.

There are three different power-down options. The output is

connected internally to GND through either a 1 kΩ resistor or

a 100 kΩ resistor, or it is left in a high impedance state (three-

state). The output stage is illustrated in

Figure 34.

The bias generator, the output amplifier, the resistor string, and

all other associated linear circuitry are shut down when the

power-down mode is activated. However, the contents of the

registers are unaffected when in power-down. The time to exit

power-down is typically 2.5 μs for V

= 5 V and 5 μs when

= 3 V (see Figure 24 for a plot).

The software power-down modes programmed by PD0 and

PD1 are overridden by the

pin. Taking this pin low puts

both DACs into power-down mode simultaneously and both

outputs are put into a high impedance state. If

is not used,

it should be tied high.

RESISTOR

STRING DAC

MPLIFIE

OUT

00472-034

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 34. Output Stage During Power-Down

AD5303/AD5313/AD5323

Rev. B | Page 20 of 28

MICROPROCESSER INTERFACING

AD5303/AD5313/AD5323 TO ADSP-2101

INTERFACE

Figure 35 shows a serial interface between the AD5303/AD5313/

AD5323 and the

ADSP-2101. The ADSP-2101 should be set up

to operate in the SPORT transmit alternate framing mode. The

ADSP-2101 sport is programmed through the SPORT control

operation, active-low framing, 16-bit word length. Transmission

is initiated by writing a word to the Tx register after the SPORT

has been enabled.

SCLK

DIN

SYNC

TFS

SCLK

ADDITIONAL PINS OMITTED FOR CLARITY

00472-035

AD5303/

AD5313/

AD5323*

ADSP-2101

Figure 35. AD5303/AD5313/AD5323 to ADSP-2101 Interface

AD5303/AD5313/AD5323 TO 68HC11/68L11

INTERFACE

Figure 36 shows a serial interface between the AD5303/

AD5313/AD5323 and the 68HC11/68L11 microcontroller.

SCK of the 68HC11/68L11 drives the SCLK of the AD5303/

AD5313/AD5323, while the MOSI output drives the serial data

line (DIN) of the DAC. The

SYNC

signal is derived from a port

line (PC7). The setup conditions for correct operation of this

interface are as follows: the 68HC11/68L11 should be con-

figured so that its CPOL bit is a 0 and its CPHA bit is a 1.

When data is being transmitted to the DAC, the

SYNC

line

is taken low (PC7). When the 68HC11/68L11 is configured

as previously mentioned, data appearing on the MOSI output

is valid on the falling edge of SCK. Serial data from the 68HC11/

68L11 is transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. Data is transmitted MSB

first. To load data to the AD5303/AD5313/ AD5323, PC7 is left

low after the first eight bits are transferred and a second serial

write operation is performed to the DAC; PC7 is taken high at

the end of this procedure.

DIN

SCLK

SYNC

PC7

SCK

MOSI

68HC11/68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5303/

AD5313/

AD5323*

Figure 36. AD5303/AD5313/AD5323 to 68HC11/68L11 Interface

AD5303/AD5313/AD5323 TO 80C51/80L51

INTERFACE

Figure 37 shows a serial interface between the AD5303/

AD5313/AD5323 and the 80C51/80L51 microcontroller. The

setup for the interface is as follows: TXD of the 80C51/80L51

drives SCLK of the AD5303/AD5313/AD5323, while RXD

drives the serial data line of the part. The

SYNC

signal is again

derived from a bit programmable pin on the port. In this case,

port line P3.3 is used. When data is to be transmitted to the

AD5303/AD5313/AD5323, P3.3 is taken low. The 80C51/80L51

transmits data only in 8-bit bytes; thus only eight falling clock

edges occur in the transmit cycle. To load data to the DAC, P3.3

is left low after the first eight bits are transmitted and a second

write cycle is initiated to transmit the second byte of data. P3.3

is taken high following the completion of this cycle. The 80C51/

80L51 output the serial data in a format that has the LSB first.

The AD5303/AD5313/AD5323 require data with MSB as the

first bit received. The 80C51/80L51 transmit routine should

take this into account.

DIN

SCLK

P3.3

TXD

RXD

80C51/80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY.

00472-037

SYNC

AD5303/

AD5313/

AD5323*

Figure 37. AD5303/AD5313/AD5323 to 80C51/80L51 Interface

AD5303/AD5313/AD5323 TO MICROWIRE

INTERFACE

Figure 38 shows an interface between the AD5303/AD5313/

AD5323 and any MICROWIRE-compatible device. Serial

data is shifted out on the falling edge of the serial clock and

is clocked into the AD5303/AD5313/AD5323 on the rising

edge of the SK.

DIN

SCLKSK

MICROWIRE*

ADDITIONAL PINS OMITTED FOR CLARITY.

00472-038

CS SYNC

AD5303/

AD5313/

AD5323*

Figure 38. AD5303/AD5313/AD5323 to MICROWIRE Interface

AD5303/AD5313/AD5323

Rev. B | Page 21 of 28

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

The AD5303/AD5313/AD5323 can be used with a wide range

of reference voltages, especially if the reference inputs are con-

figured to be unbuffered, in which case the devices offer a full,

one-quadrant multiplying capability over a reference range of

0 V to V

More typically, the AD5303/AD5313/AD5323 may be used

with a fixed precision reference voltage.

Figure 39 shows a

typical setup for the AD5303/AD5313/AD5323 when using

an external reference. If the reference inputs are unbuffered,

the reference input range is from 0 V to V

, but if the on-chip

reference buffers are used, the reference range is reduced. Suit-

able references for 5 V operation are the

AD780 and REF192

(2.5 V references). For 2.5 V operation, a suitable external

reference is the

REF191, a 2.048 V reference.

SCLK

DIN

GND

AD5303/AD5313/

AD5323

SERIAL

INTERFACE

EXT

REF

00472-039

AD780/REF192

WITH V

= 5V

OR REF191 WITH

= 2.5V

OUT

SYNC

OUT

REF

1µF

= 2.5V to 5.5

BUF A BUF B

Figure 39. AD5303/AD5313/AD5323 Using External Reference

If an output range of 0 V to V

is required when the reference

inputs are configured as unbuffered (for example, 0 V to 5 V),

the simplest solution is to connect the reference inputs to V

As this supply may not be very accurate and may be noisy, the

AD5303/AD5313/AD5323 can be powered from the reference

voltage, for example, using a 5 V reference such as the

REF195,

as shown in

Figure 40. The REF195 outputs a steady supply

voltage for the AD5303/AD5313/AD5323. The supply current

required from the

REF195 is 300 μA and approximately 30 μA

or 60 μA into each of the reference inputs (if unbuffered). This

is with no load on the DAC outputs. When the DAC outputs are

loaded, the

REF195 also needs to supply the current to the

loads. The total current required (with a 10 kΩ load on each

output) is

360 μA + 2(5 V/10 kΩ) = 1.36 mA

The load regulation of the

REF195 is typically 2 ppm/mA, which

results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA current

drawn from it. This corresponds to a 0.0007 LSB error at eight

bits and 0.011 LSB error at 12 bits.

SCLK

DIN

AD5303/AD5313/

AD5323

SERIAL

INTERFACE

REF195

00472-040

OUTPUT

SYNC

OUT

REF

1µF

GND

REF

0.1µF 10µF

GND BUF A BUF B

Figure 40. Using an REF195 as Power and Reference to the

AD5303/AD5313/AD5323

BIPOLAR OPERATION USING THE AD5303/

AD5313/AD5323

The AD5303/AD5313/AD5323 have been designed for single-

supply operation, but bipolar operation is also achievable using

the circuit shown in

Figure 41. The circuit shown has been con-

figured to achieve an output voltage range of −5 V < V

OUT

< +5 V.

Rail-to-rail operation at the amplifier output is achievable using

AD820 or OP295 as the output amplifier.

SCLK

DIN

AD5303/AD5313/

AD5323

SERIAL

INTERFACE

REF195

00472-041

SYNC

OUT

A/B

REF

A/B

1µF

GND

6V to 16

0.1µF 10µF

= 5V

+5V

–5V

10kΩ

AD820/

OP295

10kΩ

±5V

GND BUF A BUF B

OUTPUT

Figure 41. Bipolar Operation Using the AD5303/AD5313/AD5323

The output voltage for any input code can be calculated as

follows:

[

]

)/(/)()2/()( R1R2VR1R2R1DVV

REF

OUT

×−+××=

where:

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REF

is the reference voltage input, and gain bit = 0, with

REF

= 5 V

R1 = R2 = 10 kΩ and V

= 5 V,

VDV

OUT

5)2/10( −×=

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD5313WBRUZ-REEL7

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