AD5303/AD5313/AD5323
Rev. B | Page 6 of 28
AC CHARACTERISTICS
1
V
DD
= 2.5 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A, B Version
3
Parameter
2
Min Typ Max
Unit Conditions/Comments
Output Voltage Settling Time V
REF
= V
DD
= 5 V
AD5303 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xc0)
AD5313 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300)
AD5323 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xc00)
Slew Rate 0.7 V/μs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry
(011 . . . 11 to 100 . . . 00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz V
REF
= 2 V ± 0.1 V p-p, unbuffered mode
Total Harmonic Distortion −70 dB V
REF
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1
Guaranteed by design and characterization, not production tested.
2
See the Terminology section.
3
Temperature range for Version A and Version B: −40°C to +105°C.
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Limit at T
MIN,
T
MAX
Parameter
1, 2 , 3
(A, B Version)
Unit Conditions/Comments
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
0 ns min
SYNC to SCLK rising edge setup time
t
5
5 ns min Data setup time
t
6
4.5 ns min Data hold time
t
7
0 ns min
SCLK falling edge to
SYNC rising edge
t
8
100 ns min
Minimum
SYNC high time
t
9
20 ns min
LDAC pulse width
t
10
20 ns min
SCLK falling edge to
LDAC rising edge
t
11
20 ns min
CLR pulse width
t
12
4, 5
5 ns min SCLK falling edge to SDO invalid
t
13
4, 5
20 ns max SCLK falling edge to SDO valid
t
14
5
0 ns min
SCLK falling edge to
SYNC rising edge
t
15
5
10 ns min
SYNC rising edge to SCLK rising edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 4 and Figure 5.
4
These are measured with the load circuit of Figure 4.
5
Daisy-chain mode only (see Figure 47).
