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CAV25080YE-GT3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
© Semiconductor Components Industries, LLC, 2012
June, 2018 − Rev. 9
1 Publication Order Number:
CAT25080/D
CAT25080, CAT25160
EEPROM Serial 8/16-Kb SPI
Description
The CAT25080/25160 are a EEPROM Serial 8/16−Kb SPI devices
internally organized as 1024x8/2048x8 bits. They feature a 32−byte
page write buffer and support the Serial Peripheral Interface (SPI)
protocol. The device is enabled through a Chip Select (CS) input. In
addition, the required bus signals are a clock input (SCK), data input
(SI) and data output (SO) lines. The HOLD
input may be used to pause
any serial communication with the CAT25080/25160 device. These
devices feature software and hardware write protection, including
partial as well as full array protection.
Features
• 20 MHz SPI (5 V) Compatible
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 32−byte Page Write Buffer
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• 8−lead SOIC, TSSOP and 8−pad, UDFN Packages
• These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
SI
SO
CAT25080
CAT25160
SCK
V
SS
V
CC
CS
WP
HOLD
Figure 1. Functional Symbol
www.onsemi.com
PIN CONFIGURATION
SI
HOLD
V
CC
V
SS
WP
SO
CS
1
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
SOIC−8
V SUFFIX
CASE 751BD
SCK
SOIC (V), TSSOP (Y), UDFN (HU2, HU4)
TSSOP−8
Y SUFFIX
CASE 948AL
Chip SelectCS
Serial Data OutputSO
Write ProtectWP
GroundV
SS
Serial Data InputSI
Serial ClockSCK
FunctionPin Name
†
PIN FUNCTION
Hold Transmission InputHOLD
Power SupplyV
CC
UDFN−8
HU4 SUFFIX
CASE 517AZ
†The exposed pad for the UDFN packages can be left
floating or connected to Ground.
CAT25080, CAT25160
www.onsemi.com
2
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Operating Temperature −45 to +130 °C
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −0.5 to V
CC
+ 0.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter Min Units
N
END
(Note 3) Endurance 1,000,000 Program / Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C unless otherwise specified.)
Symbol
Parameter Test Conditions Min Max Units
I
CC
Supply Current Read, Write, V
CC
= 5.0 V,
SO open
10 MHz / −40°C to +85°C 2 mA
5 MHz / −40°C to +125°C 2 mA
I
SB1
Standby Current V
IN
= GND or V
CC
, CS = V
CC
,
WP
= V
CC
, V
CC
= 5.0 V
2
mA
I
SB2
Standby Current V
IN
= GND or V
CC
, CS = V
CC
,
WP
= GND, V
CC
= 5.0 V
T
A
= −40°C to +85°C 4
mA
T
A
= −40°C to +125°C 5
mA
I
L
Input Leakage Current V
IN
= GND or V
CC
−2 2
mA
I
LO
Output Leakage
Current
CS = V
CC
,
V
OUT
= GND or V
CC
T
A
= −40°C to +85°C −1 1
mA
T
A
= −40°C to +125°C −1 2
mA
V
IL
Input Low Voltage −0.5 0.3 V
CC
V
V
IH
Input High Voltage 0.7 V
CC
V
CC
+ 0.5 V
V
OL1
Output Low Voltage V
CC
> 2.5 V, I
OL
= 3.0 mA 0.4 V
V
OH1
Output High Voltage V
CC
> 2.5 V, I
OH
= −1.6 mA V
CC
− 0.8 V V
V
OL2
Output Low Voltage
V
CC
> 1.8 V, I
OL
= 150 mA
0.2 V
V
OH2
Output High Voltage
V
CC
> 1.8 V, I
OH
= −100 mA
V
CC
− 0.2 V V
Table 4. PIN CAPACITANCE (Note 2) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
Test Conditions Min Typ Max Units
C
OUT
Output Capacitance (SO) V
OUT
= 0 V 8 pF
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD) V
IN
= 0 V 8 pF
CAT25080, CAT25160
www.onsemi.com
3
Table 5. A.C. CHARACTERISTICS − Mature Product
(T
A
= −40°C to +85°C (Industrial) and T
A
= −40°C to +125°C (Extended)) (Notes 4, 7)
Symbol Parameter
V
CC
= 1.8 V − 5.5 V
V
CC
= 2.5 V − 5.5 V
T
A
= −405C to +855C
Units
Min Max Min Max
f
SCK
Clock Frequency DC 5 DC 10 MHz
t
SU
Data Setup Time 40 20 ns
t
H
Data Hold Time 40 20 ns
t
WH
SCK High Time 75 40 ns
t
WL
SCK Low Time 75 40 ns
t
LZ
HOLD to Output Low Z 50 25 ns
t
RI
(Note 5) Input Rise Time 2 2
ms
t
FI
(Note 5) Input Fall Time 2 2
ms
t
HD
HOLD Setup Time 0 0 ns
t
CD
HOLD Hold Time 10 10 ns
t
V
Output Valid from Clock Low 75 40 ns
t
HO
Output Hold Time 0 0 ns
t
DIS
Output Disable Time 50 20 ns
t
HZ
HOLD to Output High Z 100 25 ns
t
CS
CS High Time 50 20 ns
t
CSS
CS Setup Time 20 15 ns
t
CSH
CS Hold Time 30 20 ns
t
CNS
CS Inactive Setup Time 20 15 ns
t
CNH
CS Inactive Hold Time 20 15 ns
t
WPS
WP Setup Time 10 10 ns
t
WPH
WP Hold Time 100 60 ns
t
WC
(Note 6) Write Cycle Time 5 5 ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL
max
/I
OH
max
; C
L
= 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t
CSH
timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the t
CSH
is defined relative to the negative clock edge.
Table 6. POWER−UP TIMING (Notes 5, 8)
Symbol Parameter Max Units
t
PUR
Power−up to Read Operation 1 ms
t
PUW
Power−up to Write Operation 1 ms
8. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CAV25080YE-GT3

Mfr. #:
Buy CAV25080YE-GT3
Manufacturer:
ON Semiconductor
Description:
EEPROM 8KB SPI SER CMOS EEPROM
Lifecycle:
New from this manufacturer.
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