CAT25080, CAT25160
www.onsemi.com
10
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16bit address (see Table 13 for the number
of significant address bits).
After receiving the last address bit, the CAT25080/160
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS
high.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25080/160 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the full content of the status register
(New product, Rev. D) or the RDY (Ready) bit only (i.e.,
data out = FFh) for previous product revision C (Mature
product). For easy detection of the internal write cycle
completion, both during writing to the memory array and to
the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.
Figure 9. READ Timing
SCK
SI
SO
BYTE ADDRESS*
0123456789
7
6 5 4 3 2 1 0
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
2120 22 23 24 25 26 27 28 29 30
00 00 0 11
Dashed Line = mode (1, 1)
A
0
A
N
CS
* Please check the Byte Address Table (Table 13)
0
10
Figure 10. RDSR Timing
012345678 10911121314
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7 6
5
4 3 2 1 0
00000 1 01
Dashed Line = mode (1, 1)
CS
CAT25080, CAT25160
www.onsemi.com
11
Hold Operation
The HOLD input can be used to pause communication
between host and CAT25080/160. To pause, HOLD
must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS
low). During
the pause, the data output pin (SO) is tristated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD
must be taken high while SCK is low.
Design Considerations
The CAT25080/160 devices incorporate PowerOn Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after V
CC
exceeds the POR trigger level
and will power down into Reset mode when V
CC
drops
below the POR trigger level. This bidirectional POR
behavior protects the device against ‘brownout’ failure
following a temporary loss of power.
The CAT25080/160 device powers up in a write disable
state and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
After power up, the CS
pin must be brought low to enter
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS
input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
opcode will be ignored and the serial output pin (SO) will
remain in the high impedance state.
Figure 11. HOLD Timing
SCK
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
t
LZ
CS
HOLD
t
CD
t
HD
t
HD
t
CD
t
HZ
ORDERING INFORMATION (Notes 13 16)
Device Order
Number
Specific
Device
Marking*
Package Type Temperature Range
Lead
Finish
Shipping
CAT25080HU4I-GT3 S3U UDFN8EP I = Industrial (40°C to +85°C) NiPdAu
CAT25080VI-GT3 25080D SOIC8, JEDEC I = Industrial (40°C to +85°C) NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25080VE-GT3 25080D SOIC8, JEDEC E = Extended (40°C to +125°C) NiPdAu
CAT25080YI-GT3 S08D TSSOP8 I = Industrial (40°C to +85°C) NiPdAu
CAT25080YE-GT3 S08D TSSOP8 E = Extended (40°C to +125°C) NiPdAu
CAT25160HU4I-GT3 S4U UDFN8EP I = Industrial (40°C to +85°C) NiPdAu
CAT25160VI-GT3 25160D SOIC8, JEDEC I = Industrial (40°C to +85°C) NiPdAu
Tape & Reel,
3,000 Units / Reel
CAT25160VE-GT3 25160D SOIC8, JEDEC E = Extended (40°C to +125°C) NiPdAu
CAT25160YI-GT3 S16D TSSOP8 I = Industrial (40°C to +85°C) NiPdAu
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
13.All packages are RoHScompliant (Leadfree, Halogenfree).
14.The standard lead finish is NiPdAu.
15.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
16.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
17.Not recommended for new design
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
DATE 23 MAR 201
5
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.08
A1
SEATING
PLANE
NOTE 3
b
8X
0.10 C
0.05 C
A
B
DIM MIN MAX
MILLIMETERS
A 0.45 0.55
A1 0.00 0.05
b 0.20 0.30
D 2.00 BSC
D2 1.35 1.45
E 3.00 BSC
E2 1.25 1.35
e 0.50 BSC
L 0.25 0.35
1
4
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.45
3.40
1
DIMENSIONS: MILLIMETERS
1
NOTE 4
0.30
8X
DETAIL A
A3 0.13 REF
A3
A
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
L1 −−− 0.15
e
RECOMMENDED
5
1.56
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXX
AWLYWG
1
M
M
0.68
C0.10
8X
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON42552E
ON SEMICONDUCTOR STANDARD
UDFN8, 2X3 EXTENDED PAD
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2

CAV25080YE-GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
EEPROM 8KB SPI SER CMOS EEPROM
Lifecycle:
New from this manufacturer.
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