Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 9: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
V
DD
V
DD
supply voltage relative to V
SS
–0.4 1.5 V 1
V
DDQ
V
DDQ
supply voltage relative to V
SS
–0.4 1.5 V 1
V
PP
Voltage on V
PP
pin relative to V
SS
–0.4 3.0 V 2
V
IN
, V
OUT
Voltage on any pin relative to V
SS
–0.4 1.5 V
Table 10: Operating Conditions
Symbol Parameter Min Nom Max Units Notes
V
DD
V
DD
supply voltage 1.14 1.20 1.26 V 1
V
PP
DRAM activating power supply 2.375 2.5 2.75 V 2
V
REFCA(DC)
Input reference voltage –
command/address bus
0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V 3
I
VTT
Termination reference current from V
TT
–750 – 750 mA
V
TT
Termination reference voltage (DC) –
command/address bus
0.49 × V
DD
-
20mV
0.5 × V
DD
0.51 × V
DD
+
20mV
V 4
I
IN
Input leakage current; any input excluding ZQ; 0V <
V
IN
< 1.1V
–2 – 2 µA 5
I
ZQ
Input leakage current; ZQ –50 – 10 µA 6, 7
I
OZpd
Output leakage current; V
OUT
= V
DD
; DQ is disabled – – 10 µA
I
OZpu
Output leakage current; V
OUT
= V
SS
; DQ is disabled;
ODT is disabled with ODT input HIGH
–50 – – µA
I
VREFCA
V
REFCA
leakage; V
REFCA
= V
DD
/2 (after DRAM is ini-
tialized)
–2 – 2 µA 7
Notes:
1. V
DDQ
balls on DRAM are tied to V
DD
.
2. V
PP
must be greater than or equal to V
DD
at all times.
3. V
REFCA
must not be greater than 0.6 × V
DD
. When V
DD
is less than 500mV, V
REF
may be
less than or equal to 300mV.
4. V
TT
termination voltages in excess of specification limit adversely affect command and
address signals' voltage margins and reduce timing margins.
5. Command and address inputs are terminated to V
DD
/2 in the registering clock driver. In-
put current is dependent on termination resistance set in the registering clock driver.
6. Tied to ground. Not connected to edge connector.
7. Multiply by number of DRAM die on module.
8GB (x72, ECC, SR) 288-Pin DDR4 VLP MiniRDIMM
Electrical Specifications
CCMTD-341111752-10428
adf9c1gx72pkiz.pdf - Rev. D 8/18 EN
16
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