74LVT273_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 10 September 2008 4 of 17
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20
74LVT273
MR V
CC
Q0 Q7
D0 D7
D1 D6
Q1 Q6
Q2 Q5
D2 D5
D3 D4
Q3 Q4
GND CP
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1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
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74LVT273
Transparent top view
GND
(1)
Q4
D3
Q3
D4
D2 D5
Q2 Q5
Q1 Q6
D1 D6
D0 D7
Q0 Q7
GND
CP
MR
V
CC
9
12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
MR 1 master reset input (active LOW)
Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output
D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input
GND 10 ground (0 V)
CP 11 clock pulse input (active on rising edge)
V
CC
20 positive supply voltage
74LVT273_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 10 September 2008 5 of 17
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
6. Functional description
[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition;
X = Don’t care; = LOW-to-HIGH clock transition; Q0 = output as it was.
7. Limiting values
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 3. Function selection
Inputs Outputs Operating mode
MR CP Dn Qn
L X X L Reset (clear)
H h H Load 1
H l L Load 0
H L X Q0 Retain state
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +4.6 V
V
I
input voltage
[1]
0.5 +7.0 V
V
O
output voltage Output in OFF or HIGH state
[1]
0.5 +7.0 V
I
IK
input clamping current V
I
< 0 V 50 - mA
I
OK
output clamping current V
O
< 0 V 50 - mA
I
O
output current output in LOW state - 128 mA
output in HIGH state 64 - mA
T
stg
storage temperature 65 +150 °C
T
j
junction temperature
[2]
- 150 °C
P
tot
total power dissipation T
amb
= 40 °C to +85 °C
[3]
500 mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 2.7 - 3.6 V
V
I
input voltage 0 - 5.5 V
I
OH
HIGH-level output current 32 - - mA
74LVT273_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 10 September 2008 6 of 17
NXP Semiconductors
74LVT273
3.3 V octal D-type flip-flop
9. Static characteristics
I
OL
LOW-level output current - - 64 mA
T
amb
ambient temperature in free air 40 - +85 °C
t/V input transition rise and fall rate;
output enabled
- - 10 ns/V
Table 5. Recommended operating conditions
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 °C to +85 °C Unit
Min Typ
[1]
Max
V
IK
input clamping voltage V
CC
= 2.7V; I
IK
= –18 mA 1.2 0.9 - V
V
IH
HIGH-level input voltage 2.0 - - V
V
IL
LOW-level input voltage - - 0.8
V
OH
HIGH-level output voltage V
CC
= 2.7 V to 3.6V; I
OH
= 100 µAV
CC
0.2 V
CC
0.1 - V
V
CC
= 2.7 V; I
OH
= 8 mA 2.4 2.5 - V
V
CC
= 3.0 V; I
OH
= 32 mA 2.0 2.2 - V
V
OL
LOW-level output voltage V
CC
= 2.7 V; I
OL
= 100 µA 0.1 0.2 V
V
CC
= 2.7 V; I
OL
= 24 mA - 0.3 0.5 V
V
CC
= 3.0 V; I
OL
= 16 mA - 0.25 0.4 V
V
CC
= 3.0 V; I
OL
= 32 mA - 0.3 0.5 V
V
CC
= 3.0 V; I
OL
= 64 mA - 0.4 0.55 V
V
OL(pu)
power-up LOW-level
output voltage
V
CC
= 3.6 V; I
O
= 1 mA; V
I
= GND or V
CC
[2]
- 0.13 0.55 V
I
I
input leakage current input pins
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V - 1 10 µA
control pins
V
CC
= 3.6 V; V
I
=V
CC
or GND - ±0.1 ±1 µA
data pins
[3]
V
CC
= 3.6 V; V
I
=V
CC
- 0.1 1 µA
V
CC
= 3.6 V; V
I
=0V 5 1 −µA
I
OFF
power-off leakage current V
CC
= 0 V; V
I
or V
O
=0Vto4.5V - 1 ±100 µA
I
LO
output leakage current V
CC
= 3.0 V; V
O
= 5.5 V; output HIGH - 60 125 µA
I
BHL
bus hold LOW current V
CC
= 3.0 V; V
I
= 0.8 V
[4]
75 150 - µA
I
BHH
bus hold HIGH current V
CC
= 3.0 V; V
I
= 2.0 V - 150 75 µA
I
BHHO
bus hold HIGH overdrive
current
V
CC
= 3.6 V; V
I
= 0 V to 3.6 V - - 500 µA
I
BHLO
bus hold LOW overdrive
current
V
CC
= 3.6 V; V
I
= 0 V to 3.6 V 500 - - µA

74LVT273D,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Flip Flops 3.3V OCTAL D
Lifecycle:
New from this manufacturer.
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