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78M6618-MR/F/P2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
78M6618 Data Sheet DS_6618_005
10 Rev. 1.4
V3P3
V3P3 -
400mV
V3P3 - 10mV
VBIAS
0V
Battery
modes
Normal
operation,
WDT
enabled
WDT dis-
abled
V1
1.12 Real-Time Clock (RTC)
The RTC circuit is driven directly by the crystal oscillator. The RTC consists of a counter chain and output
registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of
month, month, and year (including leap years). See the 78M6618 Programmer’s Reference Manual for
more information regarding the use of the 78M6618 RTC.
1.13 Hardware Watchdog Timer
In addition to the basic watchdog timer included in the 80515 MPU, an
independent, robust, fixed-duration, watchdog timer (WDT) is included in
the device. It uses the crystal oscillator as its time base and must be
refreshed by the MPU firmware at least every 1.5 seconds. When not
refreshed on time the WDT overflows, and the part is reset as if the RESET
pin were pulled high, except that the IORAM bits will be maintained. 4096
oscillator cycles (or 125 ms) after the WDT overflow, the MPU will be
launched from program address 0x0000. Asserting ICE_E will deactivate
the WDT.
The WDT can also be disabled by tying the V1 pin to V3P3. This also
deactivates V1 power fault detection. Since there is no method in firmware
to disable the crystal oscillator or the WDT, it is guaranteed that whatever
state the part might find itself in, upon watchdog overflow, the part will be
reset to a known state.
Figure 3: Functions Defined by V1
1.14 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap re-
ference. The primary use of the temperature data is to determine the magnitude of compensation required
to offset the thermal drift in the system. See the 78M6618 Programmer’s Reference Manual for more
information regarding the use of the 78M6618 Temperature Sensor.
1.15 General Purpose Digital I/O
The 78M6618 includes up to 19 pins of general-purpose digital I/O. When configured as inputs, these
pins are 5V compatible (no current-limiting resistors are needed). On reset or power-up, all DIO pins are
inputs until they are configured for the desired direction under MPU control. The Digital I/O pins can be
categorized as follows:
• DIO1/OPT_RX, DIO2/OPT_TX (2 pins) UART/DIO pin
• DIO3 (1 pin ) Dedicated DIO pin
• DIO4/SEG24 -- DIO11/SEG31 (8 pins) LCD/DIO pins
• DIO13/SEG33 -- DIO19/SEG39 (7 pins) LCD/DIO pins
• DIO43/SEG63 (1 pin ) LCD/DIO pin
DS_6618_005 78M6618 Data Sheet
Rev. 1.4 11
1.16 LCD Drivers
The 78M6618 contains a total of 35 dedicated and multiplexed LCD drivers which are grouped as follows:
• 11 dedicated LCD segment drivers.
• 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX).
• 1 driver multiplexed with auxiliary signal CKTEST (SEG19).
• 4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI).
• 16 drivers multiplexed with general purpose DIO pins.
• 2 common drivers for multiplexing (50%, or 100% duty cycle) – always available.
With a minimum of 15 driver pins always available and a total of 35 driver pins in the maximum con-
figuration, the device is capable of driving between 30 to 70 pixels of LCD display. At eight pixels per digit,
this corresponds to 3 to 8 digits. The following dedicated and multi-use pins can be assigned as LCD
segment pins for the 78M6618:
• 11 dedicated LCD segment pins: SEG0 to SEG2, SEG7, SEG8, SEG12, SEG14 to SEG18.
• 8 dual-function pins: SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI, E_RXTX/SEG9,
E_TCLK/SEG10, E_RST/SEG11, and SEG19/CKTEST.
• 16 combined DIO and segment pins: SEG24/DIO4 to SEG31/DIO11, SEG33/DIO13 to
SEG39/DIO19, and SEG63/DIO43. Of which, DIO7/SEG27 through DIO15/SEG35 can be used for
controlling relays.
See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability
of the 78M6618 LCD drivers. See the 78M6618 Hardware Design Guidelines for more information
regarding connecting the 78M6618 LCD drivers to LCDs.
1.17 EEPROM Interface
The 78M6618 provides hardware support for an optional two-pin or a three-wire (µ-wire) EEPROM
interface.
Two-Pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is
multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins.
Three-Wire (
µ
-Wire) EEPROM Interface
A 500 kHz three-wire interface, using SDATA, SCK and a DIO pin for CS is also available.
See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability
of the 78M6618 EEPROM interfaces. See the 78M6618 Hardware Design Guidelines for more
information regarding connecting the 78M6618 EEPROM interfaces to various EEPROM.
1.18 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to directly read and write
XRAM and IORAM locations. It is also able to send commands to the MPU. The interface to the slave
port consists of the PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD
segment driver pins SEG3 to SEG6.
A typical SPI transaction is as follows. While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. A transaction consists of
an 8-bit command, a 16-bit address and then one or more bytes of data. The transaction ends when
PCSZ is raised. Some transactions may consist of a command only. The last SPI command and address
(if part of the command) are available in the IORAM.
78M6618 Data Sheet DS_6618_005
12 Rev. 1.4
The SPI port supports data transfers at up to 1 Mb/s. The SPI commands are described in Table 1 and
Figure 4 illustrates the SPI Interface read and write timing.
Table 1: SPI Command Description
Command
Description
11xx xxxx ADDR D0 ... DN
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
MPU SPI interrupt is generated
1100 0000 ADDR D0 ... DN
Output data on PSDO is read from RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
No MPU SPI interrupt is generated
10xx xxxx ADDR D0 ... DN
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
MPU SPI interrupt is generated
1000 0000 ADDR D0 ... DN
Input data on PSDI is written to RAM starting with byte at ADDR.
ADDR will auto-increment until PCSZ is raised.
No MPU SPI interrupt is generated
CMD ADDR D0 ... DN
CMD and ADDR are available to the CPU in IORAM
D0 … DN are ignored.
MPU SPI interrupt is generated
A15 A14
A1 A0C0
0 31
x
D7 D6
D1 D0 D7
D6 D1 D0
C5C6C7
x
PCSZ
PSCK
PSDI
PSDO
8 bit CMD 16 bit Address
DATA[ADDR]
DATA[ADDR+1]
7 8 23 24 32 39
Extended Read . . .
SERIAL READ
A15 A14
A1 A0C0
0 31
C5C6C7
x
PCSZ
PSCK
PSDI
PSDO
8 bit CMD 16 bit Address
DATA[ADDR]
DATA[ADDR+1]
7 8 23 24 32 39
Extended Write . . .
SERIAL WRITE
D7 D6
D1 D0 D7
D6 D1 D0
x
HI Z
HI Z
(From Host)
(From 6531)
(From Host)
(From 6531)
Figure 4: SPI Slave Port: Typical Read and Write Operations
Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU or IORAM
but not SFRs or the 80515-internal register bank. See the 78M6618 Programmer’s Reference Manual for
more information regarding the mapping and use of SPI functions.
1.19 Test Port
One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. See the
78M6618 Programmer’s Reference Manual for more information regarding the use of TMUXOUT.
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78M6618-MR/F/P2

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Buy 78M6618-MR/F/P2
Manufacturer:
Maxim Integrated
Description:
IC PWR MEASUREMENT OCTAL 68QFN
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