78M6618-MR/F/P2 Datasheet 78M6618-SOCKET68, 78M6618-IM/F, 78M6618-IMR/F | P7-P9

DS_6618_005 78M6618 Data Sheet

Rev. 1.4 7

1.2 Device Reset

When the RESET pin is pulled high, all digital activity stops. Only the oscillator and RTC module continue

to run. Additionally, all IORAM bits are set to their default states. As long as V1 (the input voltage at the

power fault block) is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the

digital section.

Once initiated, the reset mode will persist until the reset timer times out. This will occur in 4096 cycles of

the crystal clock after RESET goes low, at which time the MPU will begin executing its preboot and boot

sequences from address 0x0000.

1.3 Power Management

1.3.1 Voltage Regulator

The 78M6618 provides an on chip voltage regulator to create a 2.5V supply for the digital logic. This

regulator can be run off of the V3P3SYS or VBAT inputs depending upon power availability.

1.3.2 Power Fault Management

The 78M6618 includes both hardware and software controlled power fault management. V1 is connected

to a comparator to monitor system power fault conditions. When the output of the comparator falls

(V1<VBIAS) the device will enter BROWNOUT mode if there is sufficient voltage on VBAT. If there is not

sufficient voltage on VBAT then the part will enter RESET mode.

1.3.3 BROWNOUT

In BROWNOUT mode the AFE, CE and other analog circuits are disabled leaving only the non-metering

digital circuits running. The MPU is reduced to the crystal clock rate (32kHz). From BROWNOUT the

78M6618 SW may choose to voluntarily enter other power management modes. See the 78M6618

Programmer’s Reference Manual for more information regarding the programmability of the 78M6618

power management modes. If the overhead on VBAT is insufficient to maintain the BROWNOUT mode

then the device will attempt to enter SLEEP mode. If power is restored the device will return to normal

(mission mode) operation once the PLL has settled.

1.3.4 SLEEP Mode

SLEEP mode provides the savings in battery current as only the Oscillator, and RTC functions are active.

As the CPU is disabled in SLEEP, the device can only wake up from SLEEP by the restoration of power

or RTC autowake.

1.4 Analog Front End (AFE)

The AFE functions as a data acquisition system, controlled by the MPU. The main blocks in the AFE

consist of an input multiplexer, a delta-sigma A/D converter, a FIR(Finite Impulse Response) filter and a

voltage reference. The metrology input signals (IAIH, VA, VB, VBAT and TEMP) are multiplexed before

being sampled by the ADC. The ADC output is decimated by the FIR filter and the results are stored in

XRAM where they can be accessed by the CE and the MPU. The AFE is programmable for various

system requirements including but not limited to:

• Programmable Input Multiplexer settings

• Voltage reference, Battery and Temperature monitors inputs

• Programmable ADC sampling rate

• Programmable FIR length/resolution

78M6618 Data Sheet DS_6618_005

8 Rev. 1.4

MUX

VREF

4.9152 MHz

VBIAS

CROSS

CK32

VREF

MUX

CTRL

MUX

V3P3A

FIR

VBIAS

∆Σ ADC

CONVERTER

VREF

TEMP

VBAT

FIR_DONE

FIR_START

Figure 2: AFE Block Diagram

See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability

of the 78M6618 AFE.

1.4.1 Analog Current and Voltage Inputs

Pins IA, IB, IC, ID, IE, IF, IG, IH, VA, VB are analog inputs the AFE that provide support for measuring

current and voltage in a variety of ways. Various current sensor technologies are supported including

Current Transformers (CT), Resistive Shunts and Rogowski coils.

1.5 Digital Computation Engine (CE)

The CE, a dedicated 32-bit digital signal processor, performs the precision computations necessary to

accurately measure energy. Typically CE calculations and processes include:

• Scaling of the processed samples based on calibration coefficients.

• Frequency-insensitive delay cancellation on all channels

• 90° phase shifter (for narrowband VAR calculations).

• Monitoring of the input signal frequency (for frequency and phase information).

• Monitoring of the input signal amplitude (for sag detection).

• Multiplication of each voltage and current sample to obtain the energy per sample.

• RTM(Real Time Monitor) for debug purposes

• Pulse Generators used to output CE status indicators (e.g. SAG) directly to designated DIO pins.

Due to the custom nature and complexity of the CE, generally, pre-compiled CE code is provided by

Teridian as a part of the available reference firmware and is not modified by the user. Please contact

Teridian support for more information regarding CE code.

See the 78M6618 Programmer’s Reference Manual for more information on interfacing to and

configuration of the 78M6618 CE.

1.6 80515 MPU Core

The 78M6618 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock

cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and

execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte

instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average

performance improvement (in terms of MIPS) over the Intel



8051 device running at the same clock frequency.

See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability of

MPU Memory Organization, Special Function Registers, Interrupts, Counters, and other CPU controls.

DS_6618_005 78M6618 Data Sheet

Rev. 1.4 9

1.6.1 SFR

Several custom Special Function Registers (SFR) registers are implemented in the 78M6618’s 80515

MPU. See the 78M6618 Programmer’s Reference Manual for more information regarding the mapping of

functionality to specific SFR and IORAM addresses.

1.7 XRAM

The CE and MPU share a single, general purpose 4 KB RAM (also referred to as XRAM) for data. The

XRAM is natively accessible as 32bit words from the CE and on 8 bit boundaries from the CPU. The

XRAM is accessed by the CPU through addresses 0x0000 to 0x0FFF.

1.8 IORAM

The MPU accesses most of its external input and output functionality as well as programmable

functionality through memory mapped IO (IORAM). The IORAM is accessed by the CPU as data

addresses 0x2000 to 0x20FF. See the 78M6618 Programmer’s Reference Manual for more information

regarding the mapping of functionality to specific IORAM addresses.

1.9 FLASH

The 78M6618 includes 128 KB of on-chip Flash memory. For read/write access from the CPU, the flash

is broken into four 32 KB banks that are managed by SFR settings. For erasing of the flash memory from

the CPU the flash is segmented into individual 1024-byte pages and also controlled by SFR settings. See

the 78M6618 Programmer’s Reference Manual for more information regarding the use of flash and the

mapping of functionality to specific SFR settings.

1.9.1 Program Security

The 78M6618 has functionality to guarantee the security of the user’s MPU and CE program code. When

enabled, the security feature limits the ICE to global Flash erase operations only. All other ICE

operations are blocked. Security is enabled by MPU code that is executed in a pre-boot interval before

the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a

global erase of the Flash, followed by a chip reset.

1.10 Oscillator

The 78M6618 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do

not require a high-current oscillator circuit. The 78M6618 oscillator has been designed specifically to

handle these crystals and is compatible with their high impedance and limited power handling capability.

The oscillator is powered directly and only from the VBAT pin, which therefore must be connected to a

DC voltage source not to exceed 4 V. The oscillator requires approximately 100 nA, which is negligible

compared to the internal leakage of a battery

Since the oscillator is self-biasing, an external resistor must not be connected across the crystal.

1.11 PLL and Internal Clock Generation

Timing for the device is derived from the 32.768 kHz crystal oscillator output. The PLL and on-chip timing

functions provide several clocks which include:

• The MPU clock (CKMPU)

• The emulator clock (2 x CKMPU)

• The clock for the CE (CKCE)

• The delta-sigma ADC and FIR clock(CKADC, CKFIR)

These internal clocks can be adjusted for various programmable rates which affect device functionality.

See the 78M6618 Programmer’s Reference Manual for more information regarding the programmability

of the 78M6618 PLL and internal clock generation modules.

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