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MC74HC161ADTG

P1-P3P4-P6P7-P9P10-P12P13-P15
MC74HC161A, MC74HC163A
http://onsemi.com
10
RESET (HC161A)
RESET (HC163A)
LOAD
P0
P1
P2
P3
CLOCK (HC161A)
CLOCK (HC163A)
ENABLE P
ENABLE T
Q0
Q1
Q2
Q3
RIPPLE
CARRY
OUT
(ASYNCHRONOUS)
(SYNCHRONOUS)
12 13 14 15 0 1 2
RESET LOAD
COUNT
ENABLES
OUTPUTS
PRESET
DATA
INPUTS
INHIBIT
COUNT
Figure 12. Timing Diagram
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.
MC74HC161A, MC74HC163A
http://onsemi.com
11
P0
P1
P2
P3
ENABLE P
ENABLE T
RESET
T0
R
C
C
LOAD
LOAD
P0
Q0 Q0
Q1
Q2
Q3
RIPPLE
CARRY
OUT
V
CC
= PIN 16
GND = PIN 8
14
The flip−flops shown in the circuit diagrams are Toggle−Enable flip−flops. A Toggle−
Enable flip−flop is a combination of a D flip−flop and a T flip−flop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flip−flop. The logic level at the Pn input is then clocked to the Q output of the flip−flop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flip−flop low.
Q0
Q1
Q1
Q2
Q2
Q3
T1
R
C
C
LOAD
LOAD
P1
T2
R
C
C
LOAD
LOAD
P2
T3
R
C
C
LOAD
LOAD
P3
13
12
11
15
3
4
5
6
7
10
1
9
2
R
C
C
LOAD
LOAD
CLOCK
LOAD
Figure 13. 4−Bit Binary Counter with Synchronous Reset (MC74HC163A)
MC74HC161A, MC74HC163A
http://onsemi.com
12
INPUTS
OUTPUTS
TO MORE
LOAD
H = COUNT
L = DISABLE
H = COUNT
L = DISABLE
RESET
CLOCK
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RQ0Q1Q2Q3
RIPPLE
CARRY
OUT
LOAD
RESET
CLOCK
ENABLE P
ENABLE T
TYPICAL APPLICATIONS CASCADING
NOTE: When used in these cascaded configurations the clock f
max
guaranteed limits may not apply. Actual performance will
depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock.
OUTPUTS OUTPUTS
Figure 14. N−Bit Synchronous Counters
Figure 15. Nibble Ripple Counter
SIGNIFICANT
STAGES
INPUTS INPUTS
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RQ0Q1Q2Q3
RIPPLE
CARRY
OUT
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RQ0Q1Q2Q3
RIPPLE
CARRY
OUT
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RQ0Q1Q2Q3
RIPPLE
CARRY
OUT
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RQ0Q1Q2Q3
RIPPLE
CARRY
OUT
LOAD P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
RQ0Q1Q2Q3
RIPPLE
CARRY
OUT
TO MORE
SIGNIFICANT
STAGES
INPUTS
OUTPUTS OUTPUTS OUTPUTS
INPUTS INPUTS
P1-P3P4-P6P7-P9P10-P12P13-P15

MC74HC161ADTG

Mfr. #:
Buy MC74HC161ADTG
Manufacturer:
ON Semiconductor
Description:
Counter ICs LOG CMOS COUNTER 4BIT
Lifecycle:
New from this manufacturer.
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