MC74HC161A, MC74HC163A
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7
FUNCTION DESCRIPTION
The HC161A/163A are programmable 4−bit synchronous
counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading, and
count−enable controls.
The HC161A and HC163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.
INPUTS
Clock (Pin 2)
The internal flip−flops toggle and the output count
advances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading, occur with
the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the
internal flip−flops and appear at the counter outputs.
P0 (Pin 3) is the least−significant bit and P3 (Pin 6) is the
most−significant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These are the counter outputs. Q0 (Pin 14) is the
least−significant bit and Q3 (Pin 11) is the most−significant
bit.
Ripple Carry Out (Pin 15)
When the counter is in its maximum state, 1111, this
output goes high, providing an external look−ahead carry
pulse that may be used to enable successive cascaded
counters. Ripple Carry Out remains high only during the
maximum count state. The logic equation for this output is:
Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3
OUTPUT STATE DIAGRAMS
01234
5
6
7
89101112
13
14
15
Figure 3. Binary Counters
CONTROL FUNCTIONS
Resetting
A low level on the Reset pin (Pin 1) resets the internal
flip−flops and sets the outputs (Q0 through Q3) to a low
level. The HC161A resets asynchronously, and the HC163A
resets with the rising edge of the Clock input (synchronous
reset).
Loading
With the rising edge of the Clock, a low level on Load
(Pin 9) loads the data from the Preset Data input pins (P0,
P1, P2, P3) into the internal flip−flops and onto the output
pins, Q0 through Q3. The count function is disabled as long
as Load is low.
Count Enable/Disable
These devices have two count−enable control pins:
Enable P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Count Enable = Enable P • Enable T • Load
The count is either enabled or disabled by the control
inputs according to Table 1. In general, Enable P is a
count−enable control: Enable T is both a count−enable and
a Ripple−Carry Output control.
Table 1. Count Enable/Disable
Control Inputs Result at Outputs
Load Enable P Enable T Q0 − Q3 Ripple Carry Out
H H H Count
High when Q0−Q3
are maximum*
L H H No
Count
X L H No
Count
High when Q0−Q3
are maximum*
X X L No
Count
L
*Q0 through Q3 are maximum when Q3, Q2, Q1, Q0 = 1111.
