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AD7714ARZ-3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
2
AD7714
REV. C
–15–
CH2 CH1 CH0 AIN(+) AIN(–) Type Calibration Register Pair
0 0 0 AIN1 AIN6 Pseudo Differential Register Pair 0
0 0 1 AIN2 AIN6 Pseudo Differential Register Pair 1
0 1 0 AIN3 AIN6 Pseudo Differential Register Pair 2
0 1 1 AIN4 AIN6 Pseudo Differential Register Pair 2
1 0 0 AIN1 AIN2 Fully Differential Register Pair 0
1 0 1 AIN3 AIN4 Fully Differential Register Pair 1
1 1 0 AIN5 AIN6 Fully Differential Register Pair 2
1 1 1 AIN6 AIN6 Test Mode Register Pair 2
Mode Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 00␣ Hex
The Mode Register is an eight bit register from which data can either be read or to which data can be written. Table VIII outlines the
bit designations for the Mode Register.
Table VIII. Mode Register
MD2 MD1 MD0 G2 G1 G0 BO FSYNC
MD2 MD1 MD0 Operating Mode
0 0 0 Normal Mode; this is the normal mode of operation of the device whereby the device is performing nor-
mal conversions. This is the default condition of these bits after Power-On or RESET.
0 0 1 Self-Calibration; this activates self-calibration on the channel selected by CH2, CH1 and CH0 of the
Communications Register. This is a one step calibration sequence and when complete the part returns to
Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The DRDY output or bit goes high when
calibration is initiated and returns low when this self-calibration is complete and a new valid word is
available in the data register. The zero-scale calibration is performed at the selected gain on internally
shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an internally-
generated V
REF
/Selected Gain.
0 1 0 Zero-Scale System Calibration; this activates zero scale system calibration on the channel selected by
CH2, CH1 and CH0 of the Communications Register. Calibration is performed at the selected gain on
the input voltage provided at the analog input during this calibration sequence. This input voltage should
remain stable for the duration of the calibration. The DRDY output or bit goes high when calibration is
initiated and returns low when this zero-scale calibration is complete and a new valid word is available in
the data register. At the end of the calibration, the part returns to Normal Mode with MD2, MD1 and
MD0 returning to 0, 0, 0.
0 1 1 Full-Scale System Calibration; this activates full-scale system calibration on the selected input channel.
Calibration is performed at the selected gain on the input voltage provided at the analog input during this
calibration sequence. This input voltage should remain stable for the duration of the calibration. Once
again, the DRDY output or bit goes high when calibration is initiated and returns low when this full-scale
calibration is complete and a new valid word is available in the data register. At the end of the calibration,
the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0.
Table VII. Channel Selection
CH2–CH0 Channel Select. These three bits select a channel either for conversion or for access to calibration coefficients as
outlined in Table VII. There are three pairs of calibration registers on the part. In fully differential mode, the part
has three input channels so each channel has its own pair of calibration registers. In pseudo-differential mode, the
AD7714 has five input channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself. This can be used as
a test method to evaluate the noise performance of the part with no external noise sources. In this mode, the AIN6
input should be connected to an external voltage within the allowable common-mode range for the part. The
Power-On or RESET status of these bits is 1,0,0 selecting the differential pair AIN1 and AIN2.
AD7714
REV. C–16–
MD2 MD1 MD0 Operating Mode (continued)
1 0 0 System-Offset Calibration; this activates system-offset calibration on the channel selected by CH2, CH1
and CH0 of the Communications Register. This is a one step calibration sequence and when complete
the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The DRDY output
or bit goes high when calibration is initiated and returns low when this system offset calibration is com-
plete and a new valid word is available in the data register. For this calibration type, the zero-scale cali-
bration is performed at the selected gain on the input voltage provided at the analog input during this
calibration sequence. This input voltage should remain stable for the duration of the calibration. The
full-scale calibration is performed at the selected gain on an internally generated V
REF
/Selected Gain.
1 0 1 Background Calibration; this activates background calibration on the channel selected by CH2, CH1
and CH0 of the Communications Register. If the background calibration mode is on, then the AD7714
provides continuous self-calibration of the shorted (zeroed) inputs. This calibration takes place as part
of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six.
Its major advantage is that the user does not have to worry about recalibrating the offset of the device
when there is a change in the ambient temperature or supplies. In this mode, the zero-scale calibration
is performed at the selected gain on internally shorted (zeroed) inputs. The calibrations are interleaved
with normal conversions and the calibration registers of the device are automatically updated. Because
the background calibration does not perform full-scale calibrations, a self-calibration should be per-
formed before placing the part in the background calibration mode.
1 1 0 Zero-Scale Self-Calibration; this activates zero-scale self-calibration on the channel selected by CH2,
CH1 and CH0 of the Communications Register. This zero-scale self-calibration is performed at the
selected gain on internally shorted (zeroed) inputs. This is a one step calibration sequence and when
complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The DRDY
output or bit goes high when calibration is initiated and returns low when this zero-scale self-calibration
is complete and a new valid word is available in the data register.
1 1 1 Full-Scale Self-Calibration; this activates full-scale self-calibration on the channel selected by CH2,
CH1 and CH0 of the Communications Register. This full-scale self-calibration is performed at the
selected gain on an internally-generated V
REF
/Selected Gain. This is a one step calibration sequence and
when complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
DRDY output or bit goes high when calibration is initiated and returns low when this full-scale self-
calibration is complete and a new valid word is available in the data register.
G2 G1 G0 Gain Setting
0001
0012
0104
0118
10016
10132
11064
111128
BO Burnout Current. A 0 in this bit turns off the on-chip burnout currents. This is the default (Power-On
or RESET) status of this bit. A 1 in this bit activates the burnout currents. When active, the burnout
currents connect to the selected analog input pair, one to the AIN(+) input and one to the AIN(–) input.
FSYNC Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and
the calibration control logic are held in a reset state and the analog modulator is also held in its reset
state. When this bit goes low, the modulator and filter start to process data and a valid word is available
in 3 × 1/(output update rate), i.e., the settling time of the filter. This FSYNC bit does not affect the
digital interface and does not reset the DRDY output if it is low.
2
AD7714
REV. C
–17–
Filter Registers. Power On/Reset Status: Filter High Register: 01␣ Hex. Filter Low Register: 40␣ Hex.
There are two 8-bit Filter Registers on the AD7714 from which data can either be read or to which data can be written. Tables IX
and X outline the bit designations for the Filter Registers.
Table IX. Filter High Register (RS2–RS0 = 0, 1, 0)
B/U WL BST ZERO FS11 FS10 FS9 FS8 A Versions
B/U WL BST CLKDIS FS11 FS10 FS9 FS8 Y Versions
Table X. Filter Low Register (RS2–RS0 = 0, 1, 1)
FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0 All Versions
B/U Bipolar/Unipolar Operation. A 0 in this bit selects Bipolar Operation. This is the default (Power-On or RESET)
status of this bit. A 1 in this bit selects unipolar operation.
WL Word Length. A 0 in this bit selects 16-bit word length when reading from the data register (i.e., DRDY returns
high after 16 serial clock cycles in the read operation). This is the default (Power-On or RESET) status of this
bit. A 1 in this bit selects 24-bit word length.
BST Current Boost. A 0 in this bit reduces the current taken by the analog front end. When the part is operated with
f
CLK IN
= 1␣ MHz or at gains of 1 to 4 with f
CLK IN
= 2.4576␣ MHz, this bit should be 0 to reduce the current
drawn from AV
DD
, although the device will operate just as well with this bit at a 1. When the AD7714 is oper-
ated at gains of 8 to 128 with f
CLK IN
= 2.4576␣ MHz, this bit must be 1 to ensure correct operation of the
device. The Power-On or RESET status of this bit is 0.
ZERO To ensure correct operation of the A Versions of the part, a 0 must be written to this bit.
CLKDIS Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLKOUT
pin. When disabled, the MCLKOUT pin is forced low. This feature allows the user the flexibility of using the
MCLKOUT as a clock source for other devices in the system or for turning off the MCLKOUT as a power
saving feature. When using an external master clock or the MCLKIN pin, the AD7714 continues to have inter-
nal clocks and will convert normally with its CLKDIS bit active. When using a crystal oscillator or ceramic
resonator across the MCLK IN or MCLKOUT pins, the AD7714 clock is stopped and no conversions take
place when the CLKDIS bit is active.
FS11–FS0 Filter Selection. The on-chip digital filter provides a Sinc
3
(or (Sinx/x)
3
) filter response. The 12 bits of data
programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter and
the data rate for the part. In association with the gain selection, it also determines the output noise (and hence
the effective resolution) of the device.
The first notch of the filter occurs at a frequency determined by the relationship:
filter first notch frequency =␣ (f
CLK␣ IN
/128)/code
where code is the decimal equivalent of the code in bits FS0 to FS11 and is in the range 19 to 4,000. With the
nominal f
CLK IN
of 2.4576␣ MHz, this results in a first notch frequency range from 4.8␣ Hz to 1.01␣ kHz. To
ensure correct operation of the AD7714, the value of the code loaded to these bits must be within this range.
Failure to do this will result in unspecified operation of the device.
Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I through IV show
the effect of the filter notch frequency and gain on the effective resolution of the AD7714. The output data rate
(or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. For
example, if the first notch of the filter is selected at 50␣ Hz then a new word is available at a 50 Hz rate or every
20␣ ms. If the first notch is at 1␣ kHz, a new word is available every 1␣ ms.
The settling time of the filter to a full-scale step input change is worst case 4 × 1/(output data rate). For
example, with the first filter notch at 50␣ Hz, the settling time of the filter to a full-scale step input change is
80␣ ms max. This settling time can be reduced to 3 × 1/(output data rate) by synchronizing the step input
change to a reset of the digital filter. In other words, if the step input takes place with the SYNC input low or
the FSYNC bit high, the settling time will be 3 × 1/(output data rate) from when SYNC returns high or
FSYNC returns low. If a change of channel takes place, the settling time is 3 × 1/(output data rate) regardless of
the SYNC or FSYNC status as the part issues an internal SYNC command when requested to change channels.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –3 dB frequency = 0.262 × filter first notch frequency.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

AD7714ARZ-3

Mfr. #:
Buy AD7714ARZ-3
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition
Lifecycle:
New from this manufacturer.
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