AD7714ARZ-3 Datasheet AD7714ARZ-5, AD7714YRZ, AD7714YRUZ | P31-P33

AD7714

REV. C–30–

Figure 8. Flowchart for Setting Up and Reading from the AD7714

CONFIGURING THE AD7714

The AD7714 contains eight on-chip registers that can be

accessed via the serial interface. Communication with any of

these registers is initiated by writing to the Communications

which is used to configure all registers after a power-up or reset.

The flowchart also shows two different read options—the first

where the DRDY pin is polled to determine when an update of

the data register has taken place, the second where the DRDY

bit of the Communications Register is interrogated to see if a

data register update has taken place. Also included in the flow-

ing diagram is a series of words which should be written to the

registers for a particular set of operating conditions. These con-

ditions are test channel (AIN6/AIN6), gain of 1, burnout cur-

rent off, no filter sync, bipolar mode, 24-bit word length, boost

off and maximum filter word (4000 decimal).

START

CONFIGURE & INITIALIZE µC/µP SERIAL PORT

POWER-ON/RESET FOR AD7714

WRITE TO COMMUNICATIONS REGISTER SETTING UP

CHANNEL & SETTING UP NEXT OPERATION TO BE A

WRITE TO THE FILTER HIGH REGISTER (27 HEX)

WRITE TO FILTER HIGH REGISTER SETTING

UP REQUIRED VALUES (4F HEX)

WRITE TO FILTER LOW REGISTER SETTING

UP REQUIRED VALUES (A0 HEX)

WRITE TO MODE REGISTER SETTING UP REQUIRED

VALUES & INITIATING A CALIBRATION (20 HEX)

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A WRITE TO THE FILTER LOW REGISTER (37 HEX)

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A WRITE TO THE MODE REGISTER (17 HEX)

POLL DRDY PIN

DRDY

LOW?

YES

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A READ FROM THE DATA REGISTER (5F HEX)

READ FROM DATA REGISTER

DRDY

LOW?

POLL DRDY BIT OF COMMUNICATIONS REGISTER

YES

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO

BE A READ FROM THE DATA REGISTER (5F HEX)

READ FROM DATA REGISTER

WRITE TO COMMUNICATIONS REGISTER SETTING UP

SAME CHANNEL & SETTING UP NEXT OPERATION TO BE A

READ FROM THE COMMUNICATIONS REGISTER (0F HEX)

READ FROM COMMUNICATIONS REGISTER

AD7714

REV. C

–31–

The 68HC11 is configured in the master mode with its CPOL

bit set to a logic zero and its CPHA bit set to a logic one. When

the 68HC11 is configured like this, its SCLK line idles low

between data transfers. Therefore, the POL input of the AD7714

should be hard-wired low. For systems where it is preferable

that the SCLK idle high, the CPOL bit of the 68HC11 should

be set to a logic 1 and the POL input of the AD7714 should be

hard-wired to a logic high.

AD7714

DATA OUT

SCLK

SYNC

68HC11

RESET

DATA IN

POL

SCK

MISO

MOSI

Figure 9. AD7714 to 68HC11 Interface

The AD7714 is not capable of full duplex operation. If the

AD7714 is configured for a write operation, no data appears on

the DATA OUT lines even when the SCLK input is active.

Similarly, if the AD7714 is configured for a read operation, data

presented to the part on the DATA IN line is ignored even

when SCLK is active.

Coding for an interface between the 68HC11 and the AD7714

is given in Table XV. In this example, the DRDY output line of

the AD7714 is connected to the PC0 port bit of the 68HC11

and is polled to determine its status.

AD7714 to 8051 Interface

An interface circuit between the AD7714 and the 8XC51 mi-

crocontroller is shown in Figure 10. The diagram shows the

minimum number of interface connections with CS on the

AD7714 hard-wired low. In the case of the 8XC51 interface the

minimum number of interconnects is just two. In this scheme,

the DRDY bit of the Communications Register is monitored to

determine when the Data Register is updated. The alternative

scheme, which increases the number of interface lines to three,

is to monitor the DRDY output line from the AD7714. The

monitoring of the DRDY line can be done in two ways. First,

DRDY can be connected to one of the 8XC51’s port bits (such

as P1.0) which is configured as an input. This port bit is then

polled to determine the status of DRDY. The second scheme is

to use an interrupt driven system in which case, the DRDY

output is connected to the INT1 input of the 8XC51. For

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7714’s flexible serial interface allows for easy interface

to most microcomputers and microprocessors. The flowchart of

Figure 8 outlines the sequence which should be followed when

interfacing a microcontroller or microprocessor to the AD7714.

Figures 9, 10 and 11 show some typical interface circuits.

The serial interface on the AD7714 has the capability of operat-

ing from just three wires and is compatible with SPI interface

protocols. The three-wire operation makes the part ideal for

isolated systems where minimizing the number of interface lines

minimizes the number of opto-isolators required in the system.

The rise and fall times of the digital inputs to the AD7714

(especially the SCLK input) should be no longer than 1␣ µs.

Most of the registers on the AD7714 are 8-bit registers which

facilitates easy interfacing to the 8-bit serial ports of microcon-

trollers. Some of the registers on the part are up to 24 bits, but

data transfers to these 24-bit registers can consist of a full 24-bit

transfer or three 8-bit transfers to the serial port of the micro-

controller. DSP processors and microprocessors generally trans-

fer 16 bits of data in a serial data operation. Some of these

processors, such as the ADSP-2105, have the facility to program

the amount of cycles in a serial transfer. This allows the user to

tailor the number of bits in any transfer to match the register

length of the required register in the AD7714.

Even though some of the registers on the AD7714 are only eight

bits in length, communicating with two of these registers in

successive write operations can be handled as a single 16-bit

data transfer if required. For example, if the Mode Register is to

be updated, the processor must first write to the Communica-

tions Register (saying that the next operation is a write to the

Mode Register) and then write eight bits to the Mode Register.

This can all be done in a single 16-bit transfer if required be-

cause once the eight serial clocks of the write operation to the

Communications Register have been completed the part imme-

diately sets itself up for a write operation to the Mode Register.

AD7714 to 68HC11 Interface

Figure 9 shows an interface between the AD7714 and the

68HC11 microcontroller. The diagram shows the minimum

(three-wire) interface with CS on the AD7714 hard-wired low.

In this scheme, the DRDY bit of the Communications Register

is monitored to determine when the Data Register is updated.

An alternative scheme, which increases the number of interface

lines to four, is to monitor the DRDY output line from the

AD7714. The monitoring of the DRDY line can be done in two

ways. First, DRDY can be connected to one of the 68HC11’s

port bits (such as PC0) which is configured as an input. This

port bit is then polled to determine the status of DRDY. The

second scheme is to use an interrupt driven system in which

case, the DRDY output is connected to the IRQ input of the

68HC11. For interfaces which require control of the CS input

on the AD7714, one of the port bits of the 68HC11 (such as

PC1), which is configured as an output, can be used to drive the

CS input.

AD7714

REV. C–32–

interfaces which require control of the CS input on the AD7714,

one of the port bits of the 8XC51 (such as P1.1), which is con-

figured as an output, can be used to drive the CS input.

AD7714

DATA OUT

POL

SYNC

8XC51

RESET

DATA IN

SCLK

P3.0

P3.1

Figure 10. AD7714 to 8051 Interface

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7714 should be

connected together. The serial clock on the 8XC51 idles high

between data transfers and, therefore, the POL input of the

AD7714 should be hard-wired to a logic high. The 8XC51

outputs the LSB first in a write operation while the AD7714

expects the MSB first so the data to be transmitted has to be

rearranged before being written to the output serial register.

Similarly, the AD7714 outputs the MSB first during a read

operation while the 8XC51 expects the LSB first. Therefore, the

data that is read into the serial buffer needs to be rearranged

before the correct data word from the AD7714 is available in

the accumulator.

AD7714 to ADSP-2103/ADSP-2105 Interface

Figure 11 shows an interface between the AD7714 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface shown,

the DRDY bit of the Communications Register is again moni-

tored to determine when the Data Register is updated. The

alternative scheme is to use an interrupt driven system in which

case, the DRDY output is connected to the IRQ2 input of the

ADSP-2103/ADSP-2105. The RFS and TFS pins of the

ADSP-2103/ADSP-2105 are configured as active low outputs

and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is

also configured as an output. The POL pin of the AD7714 is

hard-wired low. Because the SCLK from the ADSP-2103/

ADSP-2105 is a continuous clock, the CS of the AD7714 must

be used to gate off the clock once the transfer is complete. The

CS for the AD7714 is active when either the RFS or TFS

outputs from the ADSP-2103/ADSP-2105 are active. The serial

clock rate on the ADSP-2103/ADSP-2105 should be limited to

3␣ MHz to ensure correct operation with the AD7714.

AD7714

DATA OUT

SYNC

ADSP-2103/2105

RESET

DATA IN

SCLK

RFS

TFS

POL

SCLK

Figure 11. AD7714 to ADSP-2103/ADSP-2105 Interface

CODE FOR SETTING UP THE AD7714

Table XV gives a set of read and write routines in C code for

interfacing the 68HC11 microcontroller to the AD7714. The

sample program sets up the various registers on the AD7714

and reads 1000 samples from the part into the 68HC11. The

setup conditions on the part are exactly the same as those out-

lined for the flowchart of Figure 8. In the example code given

here the DRDY output is polled to determine if a new valid

word is available in the output register.

The sequence of the events in this program are as follows:

1. Write to the Communications Register, setting the channel.

2. Write to the Filter High Register, setting the 4 MSBs of the

filter word and setting the part for 24-bit read, bipolar mode

with boost off.

3. Write to the Filter Low Register, setting the 8 LSBs of the

filter word.

4. Write to the Mode Register, setting the part for a gain of 1,

burnout current off, no filter synchronization and initiating a

self-calibration.

5. Poll the DRDY Output.

6. Read the data from the Data Register.

7. Loop around doing steps 5 and 6 until the specified number

of samples have been taken.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P41

AD7714ARZ-3

Mfr. #:

Buy AD7714ARZ-3

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition

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AD7714ARZ-3

AD7714ARZ-3

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