AD7714ARZ-3 Datasheet AD7714ARZ-5, AD7714YRZ, AD7714YRUZ | P22-P24

AD7714

REV. C

–21–

Table XIV. Input Sampling Frequency vs. Gain

Gain Input Sampling Freq (f

)

CLK IN

/64 (38.4␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

22 × f

CLK IN

/64 (76.8␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

44 × f

CLK IN

/64 (153.6␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

88 × f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

16 8 × f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

32 8 × f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

64 8 × f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

128 8 × f

CLK IN

/64 (307.2␣ kHz @ f

CLK IN

= 2.4576␣ MHz)

Burnout Current

The AD7714 contains two 1␣ µA currents, one source current

from AV

to AIN(+) and one sink from AIN(–) to AGND. The

currents are either both on or off depending on the BO bit of the

Mode Register. These currents can be used in checking that a

transducer has not burned out nor gone open-circuit before

attempting to take measurements on that channel. If the cur-

rents are turned on, allowed flow in the transducer, a measure-

ment of the input voltage on the analog input taken and the

voltage measured is full scale, it indicates that the transducer has

gone open-circuit; if the voltage measured is zero, it indicates

that the transducer has gone short-circuit. For normal opera-

tion, these burnout currents are turned off by writing a 0 to the

BO bit. For the source current to work correctly, the applied

voltage on AIN(+) should not go within 500␣ mV of AV

. For

the sink current to work correctly, the applied voltage on the

AIN(–) input should not go within 500␣ mV of AGND.

Bipolar/Unipolar Inputs

The analog inputs on the AD7714 can accept either unipolar or

bipolar input voltage ranges. Bipolar input ranges do not imply

that the part can handle negative voltages on its analog inputs,

since the analog input cannot go more negative than –30␣ mV to

ensure correct operation of the part. The input channels are

either fully differential or pseudo-differential (all other channels

referenced to AIN6). In either case, the input channels are

arranged in pairs with an AIN(+) and AIN(–). As a result, the

voltage to which the unipolar and bipolar signals on the AIN(+)

input are referenced is the voltage on the respective AIN(–)

input. For example, if AIN(–) is +2.5␣ V and the AD7714 is

configured for unipolar operation with a gain of 2 and a V

REF

+2.5␣ V, the input voltage range on the AIN(+) input is +2.5 V to

+3.75␣ V. If AIN(–) is +2.5␣ V and the AD7714 is configured for

bipolar mode with a gain of 2 and a V

REF

of +2.5␣ V, the analog

input range on the AIN(+) input is +1.25␣ V to +3.75 V (i.e.,

2.5␣ V ± 1.25␣ V). If AIN(–) is at AGND, the part cannot be con-

figured for bipolar ranges in excess of ±30␣ mV.

Bipolar or unipolar options are chosen by programming the B/U

bit of the Filter High Register. This programs the selected chan-

nel for either unipolar or bipolar operation. Programming the

channel for either unipolar or bipolar operation does not change

any of the input signal conditioning; it simply changes the data

output coding and the points on the transfer function where

calibrations occur.

REFERENCE INPUT

The AD7714’s reference inputs, REF␣ IN(+) and REF␣ IN(–),

provide a differential reference input capability. The common-

mode range for these differential inputs is from AGND to AV

The nominal reference voltage, V

REF

(REF␣ IN(+)␣ –REF␣ IN(–)),

for specified operation is +2.5␣ V for the AD7714-5 and +1.25␣ V

for the AD7714-3. The part is functional with V

REF

voltages

down to 1 V but with degraded performance as the output noise

will, in terms of LSB size, be larger. REF␣ IN(+) must always be

greater than REF␣ IN(–) for correct operation of the AD7714.

Both reference inputs provide a high impedance, dynamic load

similar to the analog inputs in unbuffered mode. The maxi-

mum dc input leakage current is ±1 nA over temperature and

source resistance may result in gain errors on the part. In this

case, the sampling switch resistance is 5␣ kΩ typ and the refer-

ence capacitor (C

REF

) varies with gain. The sample rate on the

reference inputs is f

CLK IN

/64 and does not vary with gain. For

gains of 1 to 8, C

REF

is 8 pF; for a gain of 16, it is 5.5 pF, for a

gain of 32, it is 4.25 pF, for a gain of 64, it is 3.625 pF and for a

gain of 128, it is 3.3125 pF.

The output noise performance outlined in Tables I through IV

is for an analog input of 0 V and is unaffected by noise on the

reference. To obtain the same noise performance as shown in

the noise tables over the full input range requires a low noise

reference source for the AD7714. If the reference noise in the

bandwidth of interest is excessive, it will degrade the perfor-

mance of the AD7714. In applications where the excitation

voltage for the bridge transducer on the analog input also de-

rives the reference voltage for the part, the effect of the noise in

the excitation voltage will be removed as the application is

ratiometric. Recommended reference voltage sources for the

AD7714-5 and AD7714Y grade with AV

= 5 V include the

AD780, REF43 and REF192 while the recommended reference

sources for the AD7714-3 and AD7714Y with AV

= 3 V

include the AD589 and AD1580. It is generally recommended

to decouple the output of these references to further reduce the

noise level.

DIGITAL FILTERING

The AD7714 contains an on-chip low-pass digital filter which

processes the output of the part’s sigma-delta modulator. There-

fore, the part not only provides the analog-to-digital conversion

function but it also provides a level of filtering. There are a

number of system differences when the filtering function is

provided in the digital domain rather than the analog domain

and the user should be aware of these.

First, since digital filtering occurs after the A-to-D conversion

process, it can remove noise injected during the conversion

process. Analog filtering cannot do this. Also, the digital filter

can be made programmable far more readily than an analog

filter. Depending on the digital filter design, this gives the user

the capability of programming cutoff frequency and output

update rate.

On the other hand, analog filtering can remove noise superim-

posed on the analog signal before it reaches the ADC. Digital

filtering cannot do this and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator

and digital filter, even though the average value of the signal is

within limits. To alleviate this problem, the AD7714 has over-

range headroom built into the sigma-delta modulator and digital

filter which allows overrange excursions of 5% above the analog

input range. If noise signals are larger than this, consideration

should be given to analog input filtering, or to reducing the

input channel voltage so that its full scale is half that of the

analog input channel full scale. This will provide an overrange

capability greater than 100% at the expense of reducing the

dynamic range by 1 bit (50%).

AD7714

REV. C–22–

The cutoff frequency of the digital filter is determined by the

value loaded to bits FS0 to FS11 in the Filter High and Filter

Low Registers. Programming a different cutoff frequency via

FS0 – FS11 does not alter the profile of the filter response; it

changes the frequency of the notches as outlined in the Filter

Registers section. The output update and first notch correspond

and are determined by the relationship:

Output Rate = f

CLK IN

/(N.128)

where N is the decimal equivalent of the word loaded to the

FS0 to FS11 bits of the Filter Registers

while the –3␣ dB frequency is determined by the relationship:

–3␣ dB frequency = 0.262

filter first notch frequency

The filter provides a linear phase response with a group delay

determined by:

Group Delay = –3

.(N.f/f

MOD

)

where N is the decimal equivalent of the word loaded to the

FS0 to FS11 bits of the Filter Registers and f

MOD

= f

CLK IN

/128.

Since the AD7714 contains this on-chip, low-pass filtering, a

settling time is associated with step function inputs and data on

the output will be invalid after a step change until the settling

time has elapsed. The settling time depends upon the output

rate chosen for the filter. The settling time of the filter to a full-

scale step input can be up to four times the output data period.

For a synchronized step input (using the SYNC or FSYNC

functions) the settling time is three times the output data pe-

riod. When changing channels on the part, the change from one

channel to the other is synchronized so the output settling time

is also three times the output data period. Thus, in switching

between channels, the output data register is not updated until

the settling time of the filter has elapsed.

Post-Filtering

The on-chip modulator provides samples at a 19.2␣ kHz output

rate with f

CLK IN

at 2.4576␣ MHz. The on-chip digital filter

decimates these samples to provide data at an output rate that

corresponds to the programmed output rate of the filter. Since

the output data rate is higher than the Nyquist criterion, the

output rate for a given bandwidth will satisfy most application

requirements. However, there may be some applications that

require a higher data rate for a given bandwidth and noise per-

formance. Applications that need this higher data rate will

require some post-filtering following the part’s digital filter.

For example, if the required bandwidth is 7.86␣ Hz but the

required update rate is 100␣ Hz, the data can be taken from the

AD7714 at the 100␣ Hz rate giving a –3 dB bandwidth of

26.2␣ Hz. Post-filtering can be applied to this to reduce the

bandwidth and output noise, to the 7.86␣ Hz bandwidth level,

while maintaining an output rate of 100␣ Hz.

Post-filtering can also be used to reduce the output noise from

the device for bandwidths below 1.26␣ Hz. At a gain of 128 and

a bandwidth of 1.26␣ Hz, the output rms noise is 140␣ nV. This

is essentially device noise or white noise and since the input is

chopped, the noise has a primarily flat frequency response. By

reducing the bandwidth below 1.26␣ Hz, the noise in the result-

ant passband can be reduced. A reduction in bandwidth by a

factor of 2 results in a reduction of approximately 1.25 in the

output rms noise. This additional filtering will result in a

longer settling time.

In addition, the digital filter does not provide any rejection at

integer multiples of the digital filter’s sample frequency. How-

ever, the input sampling on the part provides attenuation at

multiples of the digital filter’s sampling frequency so that the

unattenuated bands actually occur around multiples of the input

sampling frequency f

(as defined in Table XIV). Thus, the

unattenuated bands occur at n × f

(where n = 1, 2, 3. . .). At

these frequencies, there are frequency bands, ±f

3 dB

wide (f

3 dB

the cutoff frequency of the digital filter) at either side where

noise passes unattenuated to the output.

Filter Characteristics

The AD7714’s digital filter is a low-pass filter with a (sinx/x)

response (also called sinc

). The transfer function for this filter

is described in the z-domain by:

H(z) =

1 − Z

−N

1 − Z

−1













and in the frequency domain by:

Sin N f f

Sin f f

()

(.. )

(. )

=×

Figure 4 shows the filter frequency response for a cutoff

frequency of 2.62␣ Hz which corresponds to a first filter notch

frequency of 10␣ Hz. The plot is shown from dc to 65␣ Hz.

This response is repeated at either side of the input sampling

frequency and at either side of multiples of the input sampling

frequency.

FREQUENCY – Hz

600

–40

50302010 40

–60

–80

–100

–120

–140

–160

–180

–200

–220

–20

–240

GAIN – dB

Figure 4. Frequency Response of AD7714 Filter

The response of the filter is similar to that of an averaging filter

but with a sharper roll-off. The output rate for the digital filter

corresponds with the positioning of the first notch of the filter’s

frequency response. Thus, for the plot of Figure 4 where the

output rate is 10␣ Hz, the first notch of the filter is at 10␣ Hz. The

notches of this (sinx/x)

filter are repeated at multiples of the

first notch. The filter provides attenuation of better than 100 dB

at these notches. For the example given, if the first notch is at

10␣ Hz, there will be notches (and hence >100␣ dB rejection) at

both 50␣ Hz and 60␣ Hz.

AD7714

REV. C

–23–

value which, when normalized, is subtracted from all conversion

results. The full-scale calibration register contains a value

which, when normalized, is multiplied by all conversion results.

The offset calibration coefficient is subtracted from the result

prior to the multiplication by the full-scale coefficient. This

means that the full-scale coefficient is effectively a span or gain

coefficient.

The AD7714 offers self-calibration, system calibration and

background calibration facilities. For full calibration to occur

on the selected channel, the on-chip microcontroller must record

the modulator output for two different input conditions. These

are “zero-scale” and “full-scale” points. These points are de-

rived by performing a conversion on the different input voltages

provided to the input of the modulator during calibration. As a

result, the accuracy of the calibration can only be as good as the

noise level which the part provides in normal mode. The result

of the “zero-scale” calibration conversion is stored in the Zero

Scale Calibration Register for the appropriate channel. The

result of the “full-scale” calibration conversion is stored in the

Full-Scale Calibration Register for the appropriate channel. With

these readings, the microcontroller can calculate the offset and

the gain slope for the input to output transfer function of the

converter. Internally, the part works with 33 bits of resolution

to determine its conversion result of either 16 bits or 24 bits.

Self-Calibration

A self-calibration is initiated on the AD7714 by writing the

appropriate values (0, 0, 1) to the MD2, MD1 and MD0 bits of

the Mode Register. In the self-calibration mode with a unipolar

input range, the zero-scale point used in determining the cali-

bration coefficients is with the inputs of the differential pair

internally shorted on the part (i.e., AIN(+) = AIN(–) = Internal

Bias Voltage). The PGA is set for the selected gain (as per G2,

G1, G0 bits in the Mode Register) for this zero-scale calibration

conversion. The full-scale calibration conversion is performed at

the selected gain on an internally-generated voltage of V

REF

Selected Gain.

The duration time of the calibration is 6 × 1/Output Rate. This

is made up of 3 × 1/Output Rate for the zero-scale calibration

and 3 × 1/Output Rate for the full-scale calibration. At this time

the MD2, MD1 and MD0 bits in the Mode Register return to

0, 0, 0. This gives the earliest indication that the calibration

sequence is complete. The DRDY line goes high when calibra-

tion is initiated and does not return low until there is a valid

new word in the data register. The duration time from the cali-

bration command being issued to DRDY going low is 9 × 1/

Output Rate. This is made up of 3 × 1/Output Rate for the zero-

scale calibration, 3 × 1/Output Rate for the full-scale calibration

and 3 × 1/Output Rate for a conversion on the analog input. If

DRDY is low before (or goes low during) the calibration com-

mand write to the Mode Register, it may take up to one modu-

lator cycle (MCLK␣ IN/128) before DRDY goes high to indicate

that calibration is in progress. Therefore, DRDY should be

ignored for up to one modulator cycle after the last bit of the

calibration command is written to the Mode Register.

For bipolar input ranges in the self-calibrating mode, the se-

quence is very similar to that just outlined. In this case, the two

points are exactly the same as above but since the part is config-

ured for bipolar operation, the output code for zero differential

input is 800000 Hex in 24-bit mode.

ANALOG FILTERING

The digital filter does not provide any rejection at integer mul-

tiples of the input sampling frequency, as outlined earlier. How-

ever, due to the AD7714’s high oversampling ratio, these bands

occupy only a small fraction of the spectrum and most broad-

band noise is filtered. This means that the analog filtering re-

quirements in front of the AD7714 are considerably reduced

versus a conventional converter with no on-chip filtering. In

addition, because the part’s common-mode rejection perfor-

mance of 100␣ dB extends out to several kHz, common-mode

noise in this frequency range will be substantially reduced.

Depending on the application, however, it may be necessary to

provide attenuation prior to the AD7714 in order to eliminate

unwanted frequencies from these bands which the digital filter

will pass. It may also be necessary in some applications to pro-

vide analog filtering in front of the AD7714 to ensure that dif-

ferential noise signals outside the band of interest do not

saturate the analog modulator.

If passive components are placed in front of the AD7714, in

unbuffered mode, care must be taken to ensure that the source

impedance is low enough so as not to introduce gain errors in

the system. This significantly limits the amount of passive anti-

aliasing filtering which can be provided in front of the AD7714

when it is used in unbuffered mode. However, when the part is

used in buffered mode, large source impedances will simply

result in a small dc offset error (a 10␣ kΩ source resistance will

cause an offset error of less than 10␣ µV). Therefore, if the sys-

tem requires any significant source impedances to provide pas-

sive analog filtering in front of the AD7714, it is recommended

that the part be operated in buffered mode.

CALIBRATION

The AD7714 provides a number of calibration options which

can be programmed via the MD2, MD1 and MD0 bits of the

Mode Register. The different calibration options are outlined

in the Mode Register and Calibration Sequences sections. A

calibration cycle may be initiated at any time by writing to these

bits of the Mode Register. Calibration on the AD7714 removes

offset and gain errors from the device. A calibration routine

should be initiated on the device whenever there is a change in

the ambient operating temperature or supply voltage. It should

also be initiated if there is a change in the selected gain, filter

notch or bipolar/unipolar input range.

The AD7714 gives the user access to the on-chip calibration

registers allowing the microprocessor to read the device’s cali-

bration coefficients and also to write its own calibration coeffi-

cients to the part from prestored values in E

PROM. This gives

the microprocessor much greater control over the AD7714’s

calibration procedure. It also means that the user can verify

that the device has performed its calibration correctly by com-

paring the coefficients after calibration with prestored values in

PROM. The values in these calibration registers are 24-bit

wide. In addition, the span and offset for the part can be

adjusted by the user.

There is a significant variation in the value of these coefficients

across the different output update rates, gains and unipolar/

bipolar operation. Internally in the AD7714, these coefficients

are normalized before being used to scale the words coming out

of the digital filter. The offset calibration register contains a

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P41

AD7714ARZ-3

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Analog to Digital Converters - ADC CMOS 3V/5V 500uA 24B Signal Condition

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AD7714ARZ-3

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