Operation description SRK2001
10/20 DocID027367 Rev 4
Figure 5. Typical waveforms
Figure 6 shows the effect of this parasitic capacitance: in case at the reduced load
a capacitive current spike should trigger the turn-on, there would be a current inversion
(flowing from the output capacitor toward the SR MOSFET) causing a discharge of the
output capacitor and consequently a necessary increase of the rms rectified current, in
order to balance that discharge and this, in turn, would impair efficiency too. Therefore, the
adaptive turn-on delay is aimed to maximize the efficiency in each load operating condition.
Figure 7 shows the turn-on at the full load with minimum delay (T
D_On_min
) and at the
reduced load with increased delay (up to T
D_On.max
equal to 40% of the clock cycle).
Figure 6. Capacitive current spike effect at turn-on
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DocID027367 Rev 4 11/20
SRK2001 Operation description
20
Figure 7. Full load and light-load turn-on
At the start-up and on sleep mode exiting, the control circuit starts with a turn-on delay set to
30% of the clock cycle and progressively adapts it to the proper value. This allows reducing
system perturbation both during the start-up and while exiting the sleep mode during a fast
zero to full load transition. After the turn-on, a blanking time (equal to 50% of the clock
period) masks an undesired turn-off due to the drain-source voltage drop, consequent to
MOSFET switch on (flowing current passes from the body diode to MOSFET channel
resistance).
5.3 Turn-off
The SR MOSFET turn-off may be triggered by an adaptive turn-off mechanism (two slope
turn-off) or by the ZCD_OFF comparator (fast turn-off, see Section 5.4).
Due to the stray inductance in series with the SR MOSFET R
DS(on)
(mainly the package
stray inductance), the sensed drain-source signal is not really equal to the voltage drop
across the MOSFET R
DS(on)
, but it anticipates the time instant where the current reaches
zero, causing a premature MOSFET turn-off.
To overcome this problem (without adding any stray inductance compensation circuit), the
device uses a turn-off mechanism based on an adaptive algorithm that turns off the SR
MOSFET when the sensed drain voltage reaches zero adapting progressively the turn-off to
the maximum conduction period.
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Operation description SRK2001
12/20 DocID027367 Rev 4
Figure 8. Adaptive turn-off
Figure 8 shows this adaptive algorithm: cycle-by-cycle the conduction time is maximized
allowing in a steady-state the maximum converter efficiency.
During the start-up and on sleep mode exiting, the control circuit turns off the SR MOSFET
at 50% of the clock cycle and progressively adapts this delay in order to maximize the SR
MOSFET conduction time. This helps reducing system perturbations.
5.4 ZCD comparator
The IC is equipped with a ZCD comparator that is always ready to quickly turn-off the SR
MOSFETs, avoiding in this way current inversion, that would cause SR MOSFETs failure
and even half bridge destruction, in case of the primary controller not equipped with proper
protections.
The ZCD (zero current detection) comparator acts during fast load transitions or the short-
circuit operation and when the above resonance operation occurs. It senses that the current
has reached the zero level and triggers the gate drive circuit for a very fast MOSFET turn-off
(with a total delay time T
D_Off
).
The ZCD comparator threshold is not fixed but self-adaptive.
In the steady-state load operation and in case of slow load transitions, the turn-off is
prevalently managed by the adaptive mechanism (characterized by the two slope turn-off
driving). Instead, during fast transitions or during above resonance operation, the ZCD_OFF
comparator will take over, causing a fast MOSFET switch-off that prevents undesired
current inversions.
The ZCD_OFF comparator is blanked for 450 ns after the turn-on.
Depending on SR MOSFET choice, some premature turn-off triggered by the ZCD_OFF
comparator may be found due to the noise present on the drain-source sensed signal: this is
worse with lower RDS_ON (due to worse signal to noise ratio) and lower stray inductance of
the MOSFET package. Normally the load level where this may happen is such that the
circuit has already entered a low consumption state (for example in burst mode from primary
controller); if this is not the case, some noise reduction may be helpful, for example by using
RC snubbers across the SR MOSFETs drain-source.
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STEVAL-ISA168V1

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Power Management IC Development Tools Evaluation board: SRK2001 adaptive synchronous rectification controller for LLC resonant converters with STL140N4LLF5
Lifecycle:
New from this manufacturer.
Delivery:
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