DocID027367 Rev 4 13/20
SRK2001 Operation description
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5.5 Gate drive
The IC is provided with two high current gate drive outputs, each capable of driving one or
more N-channel power MOSFETs in parallel.
The high level voltage provided by the driver is clamped at V
GDclamp
to avoid excessive
voltage levels on the gate in case the device is supplied with a high V
CC
, thus minimizing the
gate charge provided in each switching cycle.
The two gate drivers have a pull-down capability that ensures the SR MOSFETs cannot be
spuriously turned on even at low V
CC
: in fact, the drivers have a 1 V (typ.) saturation level at
V
CC
below the turn-on threshold.
As described in the previous paragraphs, either the SR MOSFET is switched on after the
current starts flowing through the body diode, when the drain-source voltage is already low
(equal to V
F
); therefore there is no Miller effect nor switching losses at the MOSFET turn-on,
in which case the drive doesn't need to provide a fast turn-on. Also at the turn-off, during
steady-state load conditions, when the decision depends on the adaptive control circuitry,
there is no need to have a very fast drive with hard pull-down, because the current has not
yet reached zero and the operation is far from the current inversion occurrence. Moreover,
slow transitions also help reducing the perturbation introduced into the system that arise
due to the MOSFET turn-on and turn-off, contributing to improve the overall behavior of the
LLC resonant converter.
On the other side, during very fast load transitions or the short-circuit operation, when the
turn-off decision is taken by ZCD logic, the MOSFET turn-off needs to be very fast to avoid
current inversion: therefore the two gate drivers are designed to guarantee for a very short
turn-off total delay T
D_Off
.
In order to avoid current inversions, SRK2001 stops driving SR MOSFETs during any
operating condition where the converter enters deeply into the below resonance region
(i.e.: switching frequency gets lower than 60% of resonance frequency).
5.6 Intelligent automatic sleep mode
A unique feature of this IC is its intelligent automatic sleep mode. The logic circuitry is able
to detect a light-load condition for the converter and stop gate driving, reducing also IC's
quiescent consumption. This improves converter's efficiency at the light-load, where the
power losses on the rectification body diodes (or external diodes in parallel to the
MOSFETs) become lower than the power losses in the MOSFETs and those related to their
driving. The IC is also able to detect an increase of the converter's load and automatically
restarts gate driving.
The algorithm used by the intelligent automatic sleep mode is based on a dual time
measurement system: the duration of the half-switching period (i.e.: the clock cycle in
Figure 5 on page 10) and the duration of the conduction time of the synchronous rectifier.
The duration of a clock cycle is measured from the falling edge of a clock pulse to the rising
edge of the subsequent clock pulse; the duration of the SR MOSFET conduction is
measured from the moment its body diode starts conducting (drain-source voltage falling
below V
TH-ON
) to the moment the gate drive is turned off, in case the device is operating, or
to the moment the body diode ceases to conduct (drain-to-source voltage going above V
TH-
ON
) during the sleep mode operation. While at the full load the SR MOSFET conduction time
occupies almost 100% of the half-switching cycle, as the load is reduced, the conduction
duty cycle is reduced and, as it falls below D
OFF
(see data in Table 5 on page 7), the device
