MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
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Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.
Note 3: Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
149
185
Sleep mode 3
mA
Analog Supply Current I
VDD
Shutdown, clock idle, PD = OE = OV
DD
115µA
Op er ati ng , f
IN A and B
= 20.01M H z at - 0.5d BFS ;
see Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
16 mA
Sleep mode
100
Output Supply Current I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
210
µA
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
492
611
Sleep mode 10
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD
3.3 50 µW
Offset, V
DD
±5%
±3.4
Power-Supply Rejection Ratio PSRR
Gain, V
DD
±5%
±0.81
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
t
DO
C
L
= 20pF (Note 3)
4.8
7.4 ns
OE Fall to Output Enable Time
t
ENABLE
4.7
ns
OE Rise to Output Disable Time
t
DISABLE
1.2
ns
CLK Pulse-Width High t
CH
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
4.17
ns
CLK Pulse-Width Low t
CL
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
4.17
ns
Wake up from sleep mode (Note 4)
0.65
Wake-Up Time t
WAKE
Wake up from shutdown mode (Note 4)
1.2
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk f
INA or B
= 20.01MHz at -0.5dBFS
-71
dBc
Gain Matching f
INA or B
= 20.01MHz at -0.5dBFS (Note 5)
0.08 ±0.2
dB
Phase Matching f
INA or B
= 20.01MHz at -0.5dBFS (Note 6)
0.8
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V; OV
DD
= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; V
IN
= 2V
P-P
(differential with respect to COM); C
L
= 10pF at digital outputs; f
CLK
= 120MHz; T
A
=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
