REV. B
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a
Universal
LVDT Signal Conditioner
AD698
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
Single Chip Solution, Contains Internal Oscillator and
Voltage Reference
No Adjustments Required
Interfaces to Half-Bridge, 4-Wire LVDT
DC Output Proportional to Position
20 Hz to 20 kHz Frequency Range
Unipolar or Bipolar Output
Will Also Decode AC Bridge Signals
Outstanding Performance
Linearity: 0.05%
Output Voltage: 611 V
Gain Drift: 20 ppm/8C (typ)
Offset Drift: 5 ppm/8C (typ)
PRODUCT DESCRIPTION
The AD698 is a complete, monolithic Linear Variable Differen-
tial Transformer (LVDT) signal conditioning subsystem. It is
used in conjunction with LVDTs to convert transducer mechan-
ical position to a unipolar or bipolar dc voltage with a high de-
gree of accuracy and repeatability. All circuit functions are
included on the chip. With the addition of a few external passive
components to set frequency and gain, the AD698 converts the
raw LVDT output to a scaled dc signal. The device will operate
with half-bridge LVDTs, LVDTs connected in the series op-
posed configuration (4-wire), and RVDTs.
The AD698 contains a low distortion sine wave oscillator to
drive the LVDT primary. Two synchronous demodulation
channels of the AD698 are used to detect primary and second-
ary amplitude. The part divides the output of the secondary by
the amplitude of the primary and multiplies by a scale factor.
This eliminates scale factor errors due to drift in the amplitude
of the primary drive, improving temperature performance and
stability.
The AD698 uses a unique ratiometric architecture to eliminate
several of the disadvantages associated with traditional ap-
proaches to LVDT interfacing. The benefits of this new cir-
cuit are: no adjustments are necessary; temperature stability is
improved; and transducer interchangeability is improved.
The AD698 is available in two performance grades:
Grade Temperature Range Package
AD698AP –40°C to +85°C 28-Pin PLCC
AD698SQ –55°C to +125°C 24-Pin Cerdip
PRODUCT HIGHLIGHTS
1. The AD698 offers a single chip solution to LVDT signal
conditioning problems. All active circuits are on the mono-
lithic chip with only passive components required to com-
plete the conversion from mechanical position to dc voltage.
2. The AD698 can be used with many different types of posi-
tion sensors. The circuit is optimized for use with any
LVDT, including half-bridge and series opposed, (4 wire)
configurations. The AD698 accommodates a wide range of
input and output voltages and frequencies.
3. The 20 Hz to 20 kHz excitation frequency is determined by a
single external capacitor. The AD698 provides up to 24 volts
rms to differentially drive the LVDT primary, and the
AD698 meets its specifications with input levels as low as
100 millivolts rms.
4. Changes in oscillator amplitude with temperature will not af-
fect overall circuit performance. The AD698 computes the
ratio of the secondary voltage to the primary voltage to deter-
mine position and direction. No adjustments are required.
5. Multiple LVDTs can be driven by a single AD698 either in
series or parallel as long as power dissipation limits are not
exceeded. The excitation output is thermally protected.
6. The AD698 may be used as a loop integrator in the design of
simple electromechanical servo loops.
7. The sum of the transducer secondary voltages do not need to
be constant.
FUNCTIONAL BLOCK DIAGRAM
A
B
AMP
OSCILLATOR
VOLTAGE
REFERENCE
A
B
FILTER
AMP
AD698
AD698* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Data Sheet
AD698: Universal LVDT Signal Conditioner Data Sheet
REFERENCE DESIGNS
CN0301
DESIGN RESOURCES
AD698 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
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AD698–SPECIFICATIONS
REV. B
–2–
(@ T
A
= +258C, V
CM
= 0 V, and V+, V– = 615 V dc, unless otherwise noted)
AD698SQ AD698AP
Parameter Min Typ Max Min Typ Max Unit
TRANSFER FUNCTION
1
V
OUT
=
A
B
× 500 µA × R2
V
OVERALL ERROR T
MIN
to T
MAX
0.4 1.65 0.4 1.65 % of FS
SIGNAL OUTPUT CHARACTERISTICS
Output Voltage Range 611 611 V
Output Current, T
MIN
to T
MAX
11 11 mA
Short Circuit Current 20 20 mA
Nonlinearity
2
T
MIN
to T
MAX
75 6500 75 6500 ppm of FS
Gain Error
3
0.1 61.0 0.1 61.0 % of FS
Gain Drift 20 6100 20 6100 ppm/°C of FS
Output Offset 0.02 61 0.02 61 % of FS
Offset Drift 5 625 5 625 ppm/°C of FS
Excitation Voltage Rejection
4
100 100 ppm/dB
Power Supply Rejection (±12 V to ±18 V)
PSRR Gain 50 300 50 300 ppm/V
PSRR Offset 15 100 15 100 ppm/V
Common-Mode Rejection (±3 V)
CMRR Gain 25 100 25 100 ppm/V
CMRR Offset 2 100 2 100 ppm/V
Output Ripple
5
4 4 mV rms
EXCITATION OUTPUT CHARACTERISTICS (@ 2.5 kHz)
Excitation Voltage Range 2.1 24 2.1 24 V rms
Excitation Voltage (Resistors Are 1% Absolute Values)
(R1 = Open)
6
1.2 2.15 1.2 2.15 V rms
(R1 = 12.7 k) 2.6 4.35 2.6 4.35 V rms
(R1 = 487 ) 14 21.2 14 21.2 V rms
Excitation Voltage TC
7
100 100 ppm/°C
Output Current 30 50 30 50 mA rms
T
MIN
to T
MAX
40 40 mA rms
Short Circuit Current 60 60 mA
DC Offset Voltage (Differential, R1 = 12.7 k)
T
MIN
to T
MAX
30 6100 30 6100 mV
Frequency 20 20 k 20 20 k Hz
Frequency TC 200 200 ppm/°C
Total Harmonic Distortion –50 –50 dB
SIGNAL INPUT CHARACTERISTICS
A/B Ratio Usable Full-Scale Range 0.1 0.9 0.l 0.9
Signal Voltage B Channel 0.1 3.5 0.1 3.5 V rms
Signal Voltage A Channel 0.0 3.5 0.0 3.5 V rms
Input Impedance 200 200 k
Input Bias Current (BIN, AIN) 1 5 1 5 µA
Signal Reference Bias Current 2 10 2 10 µA
Excitation Frequency 0 20 k 0 20 k Hz
POWER SUPPLY REQUIREMENTS
Operating Range 13 36 13 36 V
Dual Supply Operation (±10 V Output) ±13 ±13 V
Single Supply Operation
0 V to +10 V Output 17.5 17.5 V
0 V to 10 V Output 17.5 17.5 V
Current (No Load at Signal and Excitation Outputs) 12 15 12 15 mA
T
MIN
to T
MAX
18 18 mA
OPERATING TEMPERATURE RANGE –55 +125 –40 +85 °C

AD698APZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Sensor Interface IC LVDT SIGNAL CONDITIONER
Lifecycle:
New from this manufacturer.
Delivery:
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