AD698
REV. B
–9–
FREQUENCY – Hz
0 100k100 1k 10k
10
0
–30
–60
–70
0
–10
–20
–50
–40
–360
–60
–240
–300
–420
–180
–120
GAIN – dB
PHASE SHIFT – Degrees
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
Figure 15. Gain and Phase Characteristics vs. Frequency
(0 kHz–50 kHz)
FREQUENCY – Hz
0 100 1k 10k
10
0
–30
–60
–70
–10
–20
–50
–40
0
–360
–60
–240
–300
–180
–120
GAIN – dB
PHASE SHIFT – Degrees
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
0.1µF
0.033µF
0.01µF
R2 = 81k
f
EXC
= 10kHz
Figure 16. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
Figure 16 shows a more limited frequency range with enhanced
accuracy. The figures are transfer functions with the input to be
considered as a sinusoidally varying mechanical position and the
output as the voltage from the AD698; the units of the transfer
function are volts per inch. The value of C2, C3, and C4, from
Figure 7, are all equal and designated as a parameter in the fig-
ures. The response is approximately that of two real poles.
However, there is appreciable excess phase at higher frequen-
cies. An additional pole of filtering can be introduced with a
shunt capacitor across R2, Figure 7; this will also increase phase
lag.
When selecting values of C2, C3 and C4 to set the bandwidth of
the system, a trade-off is involved. There is ripple on the “dc”
position output voltage, and the magnitude is determined by the
filter capacitors. Generally, smaller capacitors will give higher
system bandwidth and larger ripple. Figures 17 and 18 show the
magnitude of ripple as a function of C2, C3 and C4, again all
equal in value. Note also a shunt capacitor across R2, Figure 7,
is shown as a parameter. The value of R2 used was 81 k with a
Schaevitz E100 LVDT.
C2, C3, C4; C2 = C3 = C4 – µF
RIPPLE – mV rms
1k
100
0.1
0.01 0.1 101
10
1
2.5kHz, C
SHUNT
1nF
2.5kHz, C
SHUNT
10nF
Figure 17. Output Voltage Ripple vs. Filter Capacitance
C2, C3, C4; C2 = C3 = C4 – µF
RIPPLE – mV rms
1k
100
0.1
0.001 0.01 100.1
10
1
10kHz, C
SHUNT
1nF
10kHz, C
SHUNT
10nF
1
Figure 18. Output Voltage Ripple vs. Filter Capacitance
REV. B
–10–
AD698
Determining LVDT Sensitivity
LVDT sensitivity can be determined by measuring the LVDT
secondary voltages as a function of primary drive and core posi-
tion, and performing a simple computation.
Energize the LVDT at its recommended primary drive level,
V
PRI
(3 V rms for the E100). Set the core displacement to its
mechanical full-scale position and measure secondary voltages
V
A
and V
B
.
Sensitivity =
V
SECONDARY
V
PRI
× d
From Figure 19,
Sensitivity =
0.72
3V ×100 mils
= 2.4 mV /V mil
d = –100 mils d = 0
1.71V rms
0.99V rms
d = +100 mils
V
SEC
WHEN V
PRI
3V rms
V
A
V
B
Figure 19. LVDT Secondary Voltage vs. Core
Displacement
Thermal Shutdown and Loading Considerations
The AD698 is protected by a thermal overload circuit. If the die
temperature reaches 165°C, the sine wave excitation amplitude
gradually reduces, thereby lowering the internal power dissipa-
tion and temperature.
Due to the ratiometric operation of the decoder circuit, only
small errors result from the reduction of the excitation ampli-
tude. Under these conditions the signal-processing section of
the AD698 continues to meet its output specifications.
The thermal load depends upon the voltage and current deliv-
ered to the load as well as the power supply potentials. An
LVDT Primary will present an inductive load to the sine wave
excitation. The phase angle between the excitation voltage and
current must also be considered, further complicating thermal
calculations.
APPLICATIONS
Most of the applications for the AD598 can also be imple-
mented with the AD698. Please refer to the applications written
for the AD598 for a detailed explanation.
See AD598 data sheet for:
– Proving Ring-Weigh Scale
– Synchronous Operation of Multiple LVDTs
– High Resolution Position-to-Frequency Circuit
– Low Cost Setpoint Controller
– Mechanical Follower Servo Loop
– Differential Gaging and Precision Differential Gaging
AC BRIDGE SIGNAL CONDITIONER
Bridge circuits which use dc excitation are often plagued by er-
rors caused by thermocouple effects, 1/f noise, dc drifts in the
electronics, and line noise pickup. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously de-
modulate the resulting signal. The ac phase and amplitude in-
formation from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low-
pass filter.
The AD698 with the addition of a simple ac gain stage can be
used to implement an ac bridge. Figure 20 shows the connec-
tions for such a system. The AD698 oscillator provides ac
excitation for the bridge. The low level bridge signal is amplified
by the gain stage created by A1, A2 to provide a differential in-
put to the A Channel of the AD698. The signal is then synchro-
nously detected by A Channel. The B Channel is used to detect
the level of the bridge excitation. The ratio of A/B is then calcu-
lated and converted to an output voltage by R2. An optional
phase lag/lead network can be added in front of the A compara-
tor to adjust for phase delays through the bridge and the ampli-
fier, or if the phase delay is small, it can be ignored or compensated
for by a gain adjustment.
This circuit can be used for resistive bridges such as strain
gages, or for inductive or capacitive bridges that are commonly
used for pressure or flow sensors. The low level signal outputs of
these sensors are susceptible to noise and interference and are
good candidates for ac signal processing techniques.
Component Selection
Amplifiers A1, A2 will be chosen depending on the type of
bridge that is conditioned. Capacitive bridges should use an
amplifier with low bias current; a large bleeder resistor will be
required from the amplifier inputs to ground to provide a path
for the dc bias current. Resistive and inductive bridges can use a
more general purpose amplifier. The dc performance of A1, A2
are not as important as their ac performance. DC errors such as
voltage offset will be chopped out by the AD698 since they are
not synchronous to the carrier frequency.
The oscillator amplitude and span resistor for the AD698 may
be chosen by first computing the transfer function or sensitivity
of the bridge and the ac amplifier. This ratio will correspond to
the A/B term in the AD698 transfer function. For example, sup-
pose that a resistive strain gage with a sensitivity, S, of 2 mV/V
at full scale is used. Select an arbitrary target value for A/B that
is close to its maximum value such as A/B = 0.8. Then choose a
gain for the ac amplifier so that the strain gage transfer function
from excitation to output also equals 0.8. Thus the required am-
plifier gain will be [A/B]/ S; or 0.8/ 0.002 V/V = 400. Then
select values for R
S
and R
G
. For the gain stage:
AD698
REV. B
–11–
V
OUT
=
2× R
S
R
G
+1
×V
IN
Solving for V
OUT
/V
IN
= 400 and setting R
G
= 100 then:
R
S
= [400 – 1] × R
G
/2 = 19.95 k
Choose an oscillator amplitude that is in the range of 1 V to
3.5 V rms. For an input excitation level of 3 V rms, the output
signal from the amplifier gain stage will be 3.5 V rms × 0.8 V or
2.4 V rms, which is in the acceptable range.
Since A/B is known, the value of R2, the output FS resistor may
be chosen by the formula:
V
OUT
= A/B × 500 µA × R2
For a 10 V output at FS, with an A/B of 0.8; solve for R2.
R2 = 10 V [0.8 × 500 µA] = 25.0 k
This will result in a V
OUT
of 10 V for a full-scale signal from the
bridge. The other components, C1, C2, C3, C4 may be selected
by following the guidelines on general device operation men-
tioned earlier.
If a gain trim is required, then a trim resistor can be used to ad-
just either R2 or R
G
. Bridge offsets should be adjusted by a trim
network on the OFFSET 1 and OFFSET 2 pins of the AD698.
R1
C1
C2
C3
R4
R3
C4
R2
1000pF
SIGNAL
REFERENCE
R
L
V
OUT
100nF6.8µF–15V
+15V
100nF
6.8µF
AB
C
D
PHASE
LAG/LEAD
NETWORK
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–V
S
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+V
S
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
A2
R
S
A1
R
S
RESISTORS,
INDUCTORS
OR CAPACITORS
R
T
AB
CD
PHASE LEAD
R
S
C
C
R
S
R
S
R
T
A
B
CD
PHASE LAG
C
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R
S
// (R
S
+ R
T
)
R
G
DUAL
OP AMP
Figure 20. AD698 Interconnection Diagram for AC Bridge Applications

AD698APZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Sensor Interface IC LVDT SIGNAL CONDITIONER
Lifecycle:
New from this manufacturer.
Delivery:
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