AD698APZ Datasheet AD698APZ, AD698SQ, AD698AP | P4-P6

AD698

REV. B

–3–

NOTES

A and B represent the Mean Average Deviation (MAD) of the detected sine waves V

and V

. The polarity of V

OUT

is affected by the sign of the A comparator, i.e.,

multiply V

OUT

× +1 for A

COMP+

> A

COMP–

, and V

OUT

× –1 for A

COMP–

> A

COMP+

Nonlinearity of the AD698 only in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a

straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage.

See Transfer Function.

For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm.

Output ripple is a function of the AD698 bandwidth determined by C1 and C2. A 1000 pF capacitor should be connected in parallel with R2 to reduce the output

ripple. See Figures 7, 8 and 13.

R1 is shown in Figures 7, 8 and 13.

Excitation voltage drift is not an important specification because of the ratiometric operation of the AD698.

From T

MIN

to T

MAX

the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. For example, the typical overall

error for the AD698AP from T

MIN

to T

MAX

is calculated as follows: Overall Error = Gain Error at +25°C (±0.2% Full Scale) + Gain Drift from –40°C to +25°C

(20 ppm/°C × 65°C) + Offset Drift from –40°C to +25°C (5 ppm/°C × 65°C) = ±0.36% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale.

Specifications subject to change without notice.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels.

All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ORDERING GUIDE

Model Package Description Package Option

AD698AP 28-Pin PLCC P-28A

AD698SQ 24-Pin Double Cerdip Q-24A

CONNECTION DIAGRAMS

28-Pin PLCC

28 27 261234

14 15 16 17 18

TOP VIEW

(Not to Scale)

LEV1

LEV2

FREQ1

SIG REF

SIG OUT

FEEDBACK

OUT FILT

NC = NO CONNECT

AD698

BFILT1

BFILT2

AFILT1

AFILT2

+ACOMP

FREQ2

EXC2

EXC1

–V

–BIN

+BIN

–AIN

+AIN

–ACOMP

OFF1

OFF2

24-Pin Cerdip

TOP VIEW

(Not to Scale)

AD698

–V

SIG REF

OFFSET2

OFFSET1

EXC1

EXC2

LEV1

OUT FILT

FEEDBACK

SIG OUT

LEV2

FREQ1

FREQ2

BFILT1

BFILT2

–BIN

–ACOMP

AFILT2

AFILT1

+BIN

–AIN

+ACOMP

+AIN

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD698 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (+V

to –V

) . . . . . . . . . . . . . . . . . 36 V

Storage Temperature Range

P Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Q Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

AD698SQ . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

AD698AP . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

Power Dissipation Derates above +65°C

P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C

Q Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mW/°C

THERMAL CHARACTERISTICS

P Package 30°C/W 60°C/W

Q Package 26°C/W 62°C/W

REV. B

–4–

AD698

Typical Characteristics

(at +25°C and V

= ±15 V unless otherwise noted)

240

–20

140

–40–60

120

160

200

120100806040200–20

TEMPERATURE – °C

GAIN AND OFFSET PSRR – ppm/V

OFFSET PSRR 12–15V

OFFSET PSRR 15–18V

GAIN PSRR 12–15V

GAIN PSRR 15–18V

Figure 1. Gain and Offset PSRR vs. Temperature

140–40–60 120100806040200–20

–45

–35

–40

–30

–25

–20

–15

–10

–05

TEMPERATURE – °C

GAIN AND OFFSET CMRR – ppm/V

OFFSET CMRR ± 3V

GAIN CMRR ± 3V

Figure 2. Gain and Offset CMRR vs. Temperature

120

–80

140

–40

–60

–40–60

–20

120100806040200–20

TEMPERATURE – °C

TYPICAL GAIN DRIFT – ppm/°C

Figure 3. Typical Gain Drift vs. Temperature

–20

140

–10

–15

–40–60

–5

120100806040200–20

TEMPERATURE – °C

TYPICAL OFFSET DRIFT – ppm/°C

Figure 4. Typical Offset Drift vs. Temperature

AD698

REV. B

–5–

THEORY OF OPERATION

A block diagram of the AD698 along with an LVDT (linear

variable differential transformer) connected to its input is shown

in Figure 5 below. The LVDT is an electromechanical trans-

ducer—its input is the mechanical displacement of a core, and

its output is an ac voltage proportional to core position. Two

popular types of LVDTs are the half-bridge type and the series

opposed or four-wire LVDT. In both types the moveable core

couples flux between the windings. The series-opposed con-

nected LVDT transducer consists of a primary winding ener-

gized by an external sine wave reference source and two

second

ary windings connected in the series opposed configuration.

The output voltage across the series secondary increases as the core

is moved from the center. The direction of movement is detected

by measuring the phase of the output. Half-bridge LVDTs have a

single coil with a center tap and work like an autotransformer. The

excitation voltage is applied across the coil; the voltage at the center

tap is proportional to position. The device behaves similarly to a

resistive voltage divider.

AMP

OSCILLATOR

VOLTAGE

REFERENCE

FILTER

AMP

AD698

Figure 5. Functional Block Diagram

The AD698 energizes the LVDT coil, senses the LVDT output

voltages and produces a dc output voltage proportional to core

position. The AD698 has a sine wave oscillator and power am-

plifier to drive the LVDT. Two synchronous demodulation

stages are available for decoding the primary and secondary

voltages. A decoder determines the ratio of the output signal

voltage to the input drive voltage (A/B). A filter stage and out-

put amplifier are used to scale the resulting output.

The oscillator comprises a multivibrator that produces a triwave

output. The triwave drives a sine shaper that produces a low dis-

tortion sine wave. Frequency and amplitude are determined by a

single resistor and capacitor. Output frequency can range from

20 Hz to 20 kHz and amplitude from 2 V to 24 V rms. Total har-

monic distortion is typically –50 dB.

The AD698 decodes LVDTs by synchronously demodulating

the amplitude modulated input (secondaries), A, and a fixed in-

put reference (primary or sum of secondaries or fixed input), B.

A common problem with earlier solutions was that any drift in

the amplitude of the drive oscillator corresponded directly to a

gain error in the output. The AD698, eliminates

these errors by

calculating the ratio of the LVDT output to its input excitation in

order to cancel out any drift effects. This device differs from the

AD598 LVDT signal conditioner in that it implements a different

circuit transfer function and does not require the sum of the LVDT

secondaries (A + B) to be constant with stroke length.

The AD698 block diagram is shown below. The inputs consist

of two independent synchronous demodulation channels. The B

channel is designed to monitor the drive excitation to the LVDT.

The full wave rectified output is filtered by C2 and sent to the

computational circuit. Channel A is identical except that the

comparator is pinned out separately. Since the A channel may

reach 0 V output at LVDT null, the A channel demodulator is

usually triggered by the primary voltage (B Channel). In addi-

tion, a phase compensation network may be required to add a

phase lead or lag to the A Channel to compensate for the LVDT

primary to secondary phase shift. For half-bridge circuits the

phase shift is noncritical, and the A channel voltage is large

enough to trigger the demodulator.

AD698

COMP

±1

FILTER

CHANNEL

–BIN

+BIN

DUTY CYCLE

DIVIDER

A/B = 1 = 100%

DUTY

±1

–ACOMP

+ACOMP

–AIN

+AIN

FILTER

DEMODULATOR

CHANNEL

OFF 2

OFF 1

BFILT1

BFILT2

OUT

IREF

500µA

OUT

FILTER

–V

AFILT2AFILT1

V/I

COMP

V/I

Figure 6. AD698 Block Diagram

Once both channels are demodulated and filtered a division cir-

cuit, implemented with a duty cycle multiplier, is used to calcu-

late the ratio A/B. The output of the divider is a duty cycle.

When A/B is equal to 1, the duty cycle will be equal to 100%.

(This signal can be used as is if a pulse width modulated output

is required.) The duty cycle drives a circuit that modulates and

filters a reference current proportional to the duty cycle. The

output amplifier scales the 500 µA reference current converting

it to a voltage. The output transfer function is thus:

OUT

= I

REF

× A/B × R2, where I

REF

= 500 µA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AD698APZ

Mfr. #:

Buy AD698APZ

Manufacturer:

Analog Devices Inc.

Description:

Sensor Interface IC LVDT SIGNAL CONDITIONER

Lifecycle:

New from this manufacturer.

Delivery:

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AD698APZ

AD698APZ

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