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NB3W800LMNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NB3W800L
www.onsemi.com
13
Buffer Power−Up State Machine
Table 19. BUFFER POWER−UP STATE MACHINE
State Description
0
3.3 V Buffer power off
1 After 3.3 V supply is detected to rise above 3.135 V, the buffer enters State 1 and initiates a 0.1 ms–0.3 ms delay.
2 Buffer waits for a valid clock on the CLK input and PWRDN# de−assertion (or PWRGD assertion low to high)
3 Once the PLL is locked to the CLK_IN input clock, the buffer enters state 3 and enables outputs for normal operation.
(Notes 57, 58)
57.The total power up latency from power on to all outputs active must be less than 1.8 ms (assuming a valid clock is present on CLK_IN input).
58.If power is valid and powerdown is de−asserted (PWRGD asserted) but no input clocks are present on the CLK_IN input, DIF clocks must
remain disabled. Only after valid input clocks are detected, valid power, PWRDN# de−asserted (PWRGD asserted) with the PLL
locked/stable and the DIF outputs enabled.
Figure 8. Buffer Power−Up State Diagram
State 0 State 3
Power Off
Normal
Operation
State 1
Delay
0.1 ms − 0.3 ms
State 2
Powerdown Asserted
Wait for input
clock and
powerdown
de−assertion
No input clock
Device Power−Up Sequence
Follow the power−up sequence below for proper device
functionality:
1. PWRGD/PWRDN# pin must be Low.
2. Assign remaining control pins to their required
state (100M_133M#, HBW_BYPASS_LBW#,
SDA, SCL)
3. Apply power to the device.
4. Once the VDD pin has reached a valid VDDmin
level (3.3V −5%), the PWRGD/PWRDN# pin
must be asserted High. See Figure 9.
Note: If no clock is present on the CLK_IN/CLK_IN#
pins when device is powered up, there will be no clock on
DIF/DIF# outputs.
Figure 9. PWRGD and VDD Relationship Diagram
NB3W800L
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14
General SMBus Serial Interface Information for NB3W800L
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• Clock(device) will acknowledge
• Controller (host) sends the beginning byte location = N
• Clock(device) will acknowledge
• Controller (host) sends the byte count = X
• Clock(device) will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X−1
• Clock(device) will acknowledge each byte one at a
time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host) Clock (Device)
T starT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X − 1
ACK
P stoP bit
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• Clock(device) will acknowledge
• Controller (host) sends the beginning byte location = N
• Clock(device) will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• Clock(device) will acknowledge
• Clock(device) will send the data byte count = X
• Clock(device) sends Byte N+X−1
• Clock(device) sends Byte 0 through Byte X (if X
(H)
was written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host) Clock (Device)
T starT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count = X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
P stoP bit
NB3W800L
www.onsemi.com
15
Table 20. SMBus TABLE: PLL MODE, AND FREQUENCY SELECT REGISTER
Byte 0 Pin # Name Control Function Type 0 1 Default
Bit 7 48 PLL Mode 1 PLL Operating Mode Rd back 1 R
See PLL Operating Mode
Readback Table
Latched at power up
Bit 6 48 PLL Mode 0 PLL Operating Mode Rd back 0 R Latched at power up
Bit 5 Reserved 0
Bit 4 Reserved 0
Bit 3 PLL_SW_EN Enable S/W control of PLL BW RW HW Latch SMBus Control 0
Bit 2 PLL Mode 1 PLL Operating Mode 1 RW
See PLL Operating Mode
Readback Table
1
Bit 1 PLL Mode 0 PLL Operating Mode 0 RW 1
Bit 0 47 100M_133M# Frequency Select Readback R 133 MHz 100 MHz Latched at power up
NOTE: Setting bit 3 to ‘1’ allows the user to overide the Latch value from pin 48 via use of bits 2 and 1. Use the values from the PLL
Operating Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 48. A warm reset of the
system will have to accomplished if the user changes these bits.
Table 21. SMBus TABLE: OUTPUT CONTROL REGISTER
Byte 1 Pin # Name Control Function Type 0 1 Default
Bit 7 32/33 DIF_5_En
Output Control - ‘0’ overrides OE# pin
RW
Low/Low Enable
1
Bit 6 28/29 DIF_4_En
Output Control - ‘0’ overrides OE# pin
RW 1
Bit 5 25/26 DIF_3_En
Output Control - ‘0’ overrides OE# pin
RW 1
Bit 4 21/22 DIF_2_En
Output Control - ‘0’ overrides OE# pin
RW 1
Bit 3 Reserved 1
Bit 2 16/17 DIF_1_En
Output Control - ‘0’ overrides OE# pin
RW
Low/Low Enable
1
Bit 1 13/14 DIF_0_En
Output Control - ‘0’ overrides OE# pin
RW 1
Bit 0 Reserved 1
Table 22. SMBus TABLE: OUTPUT CONTROL REGISTER
Byte 2 Pin # Name Control Function Type 0 1 Default
Bit 7 Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 Reserved 0
Bit 3 Reserved 1
Bit 2 39/40 DIF_7_En
Output Control - ‘0’ overrides OE# pin
RW Low/Low Enable 1
Bit 1 Reserved 1
Bit 0 35/36 DIF_6_En
Output Control - ‘0’ overrides OE# pin
RW Low/Low Enable 1
Table 23. SMBus TABLE: RESERVED REGISTER
Byte 3 Pin # Name Control Function Type 0 1 Default
Bit 7 Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 Reserved 0
Bit 3 Reserved 0
Bit 2 Reserved 0
Bit 1 Reserved 0
Bit 0 Reserved 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NB3W800LMNG

Mfr. #:
Buy NB3W800LMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3 V 100/133 MHZ DIFFERE
Lifecycle:
New from this manufacturer.
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