OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NB3W800LMNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NB3W800L
www.onsemi.com
7
Table 12. DIF 0.7 V AC TIMING CHARACTERISTICS (Non−Spread or −0.5% Spread Spectrum Mode)
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= 0°C * 70°C), See Test Loads for Loading Conditions.
Symbol
Parameter
CLK = 100 MHz, 133.33 MHz
Unit
Min Max
Tstab (Note 32) Clock Stabilization Time 1.8 ms
Laccuracy (Notes 15, 19, 27, 33) Long Accuracy 100 ppm
Tabs (Notes 15, 16, 19) Absolute
Min/Max
Host CLK
Period
No Spread
9.94900 for 100 MHz 10.05100 for 100 MHz
ns
7.44925 for 133 MHz 7.55075 for 133 MHz
−0.5% Spread
9.49900 for 100 MHz 10.10126 for 100 MHz
7.44925 for 133 MHz 7.58845 for 133 MHz
Slew_rate (Notes 13, 15, 19) DIFF OUT Slew_rate 1.0 4.0 V/ns
DTrise / DTfall (Notes 15, 19, 29)
Rise and Fall Time Variation 125 ps
Rise/Fall Matching (Notes 15, 19, 30, 31) 20 %
VHigh (Notes 15, 18, 21)
Voltage High (typ 0.70 Volts)
660 850 mV
VLow (Notes 15, 18, 22)
Voltage Low (typ 0.0 Volts)
−150 150 mV
Vmax (Note 18) Maximum Voltage 1150 mV
Vcross absolute (Notes 12, 14, 15, 18, 25) Absolute Crossing Point Voltages 250 550 mV
Vcross relative (Notes 15, 17, 18, 25) Relative Crossing Point Voltages Calc Calc
Total D Vcross (Notes 15, 18, 26)
Total Variation of Vcross
Over All Edges
140 mV
Vovs (Notes 15, 18, 23) Maximum Voltage (Overshoot) Vhigh + 0.3 V
Vuds (Notes 15, 18, 24) Maximum Voltage (Undershoot) Vlow − 0.3 V
12.Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.
13.Measurment taken from differential waveform on a component test board. The slew rate is measured from −150 mV to +150 mV on the
differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge
Only valid for Rising CLK_IN and Falling CLK_IN#. Signal must be monotonic through the Vol to Voh region for Trise and Tfall.
14.This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
15.Test configuration is; Rs = 27 W, 2 pF for 85 W transmission line.
16.The average period over any 1 ms period of time must be greater than the minimum and less than the maximum specified period.
17.Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg − 0.700), Vcross(rel) Max = 0.550 − 0.5 (0.700
– Vhavg)
18.Measurement taken from Single Ended waveform.
19.Measurement taken from differential waveform. Bypass mode, input duty cycle = 50%.
20.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
21.VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
22.VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
23.Overshoot is defined as the absolute value of the maximum voltage.
24.Undershoot is defined as the absolute value of the minimum voltage.
25.The crossing point must meet the absolute and relative crossing point specifications simultaneously.
26.DVcross is defined as the total variation of all crossing voltages of Rising DIF and Falling DIF#. This is the maximum allowed variance in
Vcross for any particular system.
27.Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz.
28.Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz.
29.Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
30.Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of DIF versus the falling edge rate
(average) of DIF#. Measured in a ±75 mV window around the crosspoint of DIF and DIF#.
31.Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
32.This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the time that stable clocks
are output from the buffer chip (PLL locked).
33.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy
requirements. The NB3W800L itself does not contribute to ppm error.
NB3W800L
www.onsemi.com
8
Table 13. ELECTRICAL CHARACTERISTICS – Current Consumption
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= 0°C − 70°C), See Test Loads for Loading Conditions. (Note 35)
Symbol
Parameter Conditions Min Typ Max Units
I
DDVDD
Operating Current (Note 34)
133 MHz, VDD rail 94 105 mA
I
DDVDDA
133 MHz, VDDA + VDDR rail, PLL Mode 38 50 mA
I
DDVDDPD
Powerdown Current (Note 34)
Power Down, VDD Rail 2.0 3.5 mA
I
DDVDDAPD
Power Down, VDDA Rail 0.5 1.0 mA
34.Guaranteed by design and characterization, not tested in production.
35.C
L
= 2 pF with RS = 27 W for Zo = 85 W differential trace impedance.
Table 14. ELECTRICAL CHARACTERISTICS – Skew and Differential Jitter Parameters
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= 0°C − 70°C), See Test Loads for Loading Conditions.
Symbol
Parameter Conditions Min Typ Max Units
t
SPO_PLL
CLK_IN, DIF[x:0]
(Notes 36, 37, 39, 40, 43)
Input−to−Output Skew in PLL mode
nominal value @ 25°C, 3.3 V
−100 100 ps
t
PD_BYP
CLK_IN, DIF[x:0]
(Notes 36, 37, 39, 40, 43)
Input−to−Output Skew in Bypass mode
nominal value @ 25°C, 3.3 V
2.5 4.5 ns
t
DSPO_PLL
CLK_IN, DIF[x:0]
(Notes 36, 37, 39, 40, 43)
Input−to−Output Skew Varation in PLL mode
across voltage and temperature
−100 100 ps
t
DSPO_BYP
CLK_IN, DIF[x:0]
(Notes 36, 37, 39, 40, 43)
Input−to−Output Skew Varation in Bypass
mode across voltage and temperature
−250 250 ps
t
SKEW_ALL
DIF{x:0]
(Notes 36, 37, 39, 43)
Output−to−Output Skew across all outputs
(Common to Bypass and PLL mode)
50 ps
j
peak−hbw
PLL Jitter Peaking
(Notes 36, 42, 43)
HBW_BYP_LBW# = 1 2.5 dB
j
peak−lbw
PLL Jitter Peaking
(Notes 36, 42, 43)
HBW_BYP_LBW# = 0 2 dB
pll
HBW
PLL Bandwidth
(Notes 36, 43, 44)
HBW_BYP_LBW# = 1 2 3 4 MHz
pll
LBW
PLL Bandwidth
(Notes 36, 43, 44)
HBW_BYP_LBW# = 0 0.7 1 1.4 MHz
t
DC
Duty Cycle (Note 36, 46) Measured differentially, PLL and Bypass Mode 45 50 55 %
t
DCD
Duty Cycle Distortion
(Notes 36, 45)
Measured differentially, Bypass Mode
@ 100 MHz
−2 0 2 %
t
jcyc−cyc
Jitter, Cycle to cycle
(Notes 36, 46)
PLL mode 50 ps
Additive Jitter in Bypass Mode 50 ps
36.C
L
= 2 pF with RS = 27 W for Zo = 85 W differential trace impedance. Input to output skew is measured at the first output edge following the
corresponding input.
37.Measured from differential cross−point to differential cross−point. This parameter can be tuned with external feedback path, if present.
38.All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it.
39.This parameter is deterministic for a given device
40.Measured with scope averaging on to find mean value.
41.t is the period of the input clock
42.Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
43.Guaranteed by design and characterization, not tested in production.
44.Measured at 3 db down or half power point.
45.Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
46.Measured from differential waveform. Bypass mode, input duty cycle = 50%.
NB3W800L
www.onsemi.com
9
Table 15. ELECTRICAL CHARACTERISTICS – PHASE JITTER PARAMETERS
(V
DD
= V
DDA
= 3.3 V ±5%, TA = 0°C − 70°C), See Test Loads for Loading Conditions. (Note 35)
Symbol
Parameter Conditions Min Typ Max Units
t
jphPCIeG1
Phase Jitter, PLL Mode
(Note 47)
PCIe Gen 1 (Notes 48, 49) 13 86 ps (p−p)
t
jphPCIeG2
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Note 48)
0.25 3.0 ps (rms)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz) (Note 48)
1.05 3.1 ps (rms)
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Notes 48, 50)
0.21 1.0 ps (rms)
t
jphPCIeG4
PCIe Gen 4
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Notes 48, 50)
0.21 0.5 ps (rms)
t
jphUPI
UPI
(9.6 Gb/s, 10.4 Gb/s or 11.2 Gb/s, 100 MHz, 12 UI)
0.7 1.0 ps (rms)
t
jphQPI_SMI
QPI & SMI
(100 MHz or 133 MHz, 4.8 Gb/s, 6.4 Gb/s 12 UI)
(Note 51)
0.14 0.5 ps (rms)
QPI & SMI
(100 MHz, 8.0 Gb/s, 12 UI) (Note 51)
0.1 0.3 ps (rms)
QPI & SMI
(100 MHz, 9.6 Gb/s, 12 UI) (Note 51)
0.08 0.2 ps (rms)
t
jphPCIeG1
Additive Phase Jitter,
Bypass mode
(Note 47)
PCIe Gen 1 (Notes 48, 49) 10 ps (p−p)
t
jphPCIeG2
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Notes 48, 52)
0.3 ps (rms)
PCIe Gen 2 High Band 1.5 MHz < f < Nyquist
(50 MHz) (Notes 48, 52)
0.6 ps (rms)
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2−4 MHz, 2−5 MHz,
CDR = 10 MHz) (Notes 48, 50, 52)
0.2 ps (rms)
t
jphQPI_SMI
QPI & SMI
(100 MHz or 133 MHz, 4.8 Gb/s,
6.4 Gb/s 12 UI) (Notes 51, 52)
0.2 ps (rms)
QPI & SMI
(100 MHz, 8.0 Gb/s, 12 UI) (Notes 51, 52)
0.1 ps (rms)
QPI & SMI
(100 MHz, 9.6 Gb/s, 12 UI) (Notes 51, 52)
0.1 ps (rms)
47.Applies to all outputs.
48.See http://www.pcisig.com for complete specs
49.Sample size of at least 100K cycles. This figures extrapolates to 108ps pk−pk @ 1M cycles for a BER of 1−12.
50.Subject to final ratification by PCI SIG.
51.Calculated from Intel−supplied Clock Jitter Tool v 1.6.3
52.For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)
2
= (total jittter)
2
- (input jitter)
2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NB3W800LMNG

Mfr. #:
Buy NB3W800LMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3 V 100/133 MHZ DIFFERE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet