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NB3W800LMNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
NB3W800L
www.onsemi.com
4
Table 8. PIN DESCRIPTIONS
Pin # DescriptionTypePin Name
17 DIF1# OUT 0.7 V differential complementary clock output
18 OE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull−down.
1 =disable outputs, 0 = enable outputs
19 VDD PWR Power supply, nominal 3.3 V
20 NC N/A No Connection.
21 DIF2 OUT 0.7 V differential true clock output
22 DIF2# OUT 0.7 V differential complementary clock output
23 OE2# IN Active low input for enabling DIF pair 2. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
24 OE3# IN Active low input for enabling DIF pair 3. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
25 DIF3 OUT 0.7 V differential true clock output
26 DIF3# OUT 0.7 V differential complementary clock output
27 VDD PWR Power supply, nominal 3.3 V
28 DIF4 OUT 0.7 V differential true clock output
29 DIF4# OUT 0.7 V differential complementary clock output
30 OE4# IN Active low input for enabling DIF pair 4. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
31 OE5# IN Active low input for enabling DIF pair 5. This pin has an internal pull−down.
1 =disable outputs, 0 = enable outputs
32 DIF5 OUT 0.7 V differential true clock output
33 DIF5# OUT 0.7 V differential complementary clock output
34 VDD PWR Power supply, nominal 3.3 V
35 DIF6 OUT 0.7 V differential true clock output
36 DIF6# OUT 0.7 V differential complementary clock output
37 OE6# IN Active low input for enabling DIF pair 6. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
38 VDD PWR Power supply, nominal 3.3 V
39 DIF7 OUT 0.7 V differential true clock output
40 DIF7# OUT 0.7 V differential complementary clock output
41 OE7# IN Active low input for enabling DIF pair 7. This pin has an internal pull−down.
1 = disable outputs, 0 = enable outputs
42 VDD PWR Power supply, nominal 3.3 V
43 NC N/A No Connection.
44 VDDA PWR 3.3 V power for the PLL core.
45 NC N/A No Connection.
46 NC N/A No Connection.
47 100M_133M# IN 3.3 V Input to select operating frequency. See Functionality Table for Definition
48 HBW_BYP_LBW# IN Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
49 GND PWR EPAD, must be connected to Ground
NB3W800L
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Table 9. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min Typ Max Units
VDD, VDDA 3.3 V Supply Voltage (Notes 1, 2) VDD for core logic and PLL 4.6 V
V
IL
Input Low Voltage (Note 1) GND−0.5 V
V
IH
Input High Voltage (Note 1) Except for SMBus interface V
DD
+ 0.5 V
V
IHSMB
Input High Voltage (Note 1) SMBus clock and data pins 5.5 V
Ts Storage Temperature (Note 1) −65 150 °C
Tj Junction Temperature (Note 1) 125 °C
ESD prot Input ESD protection (Note 1) Human Body Model 2000 V
q
JA
Thermal Resistance, Junction−to−Ambient
Still air 17 °C/W
q
JC
Thermal Resistance, Junction−to−Case 7 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Guaranteed by design and characterization, not tested in production.
2. Operation under these conditions is neither implied nor guaranteed.
Table 10. ELECTRICAL CHARACTERISTICS–CLOCK INPUT PARAMETERS (HCSL−COMPATIBLE)
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= 0°C * 70°C), See Test Loads for Loading Conditions. (Note 5)
Symbol
Parameter Conditions Min Typ Max Units
V
IHCLK_IN
Input High Voltage - CLK_IN (Note 3)
Differential inputs
(single−ended measurement)
600 800 1150 mV
V
ILCLK_IN
Input Low Voltage - CLK_IN (Note 3)
Differential inputs
(single−ended measurement)
V
SS
- 300
0 300 mV
V
COM
Input Common Mode
Voltage - CLK_IN (Note 3)
Common Mode Input Voltage
(Single−ended measurement)
300 1000 mV
V
SWING
Input Amplitude - CLK_IN (Note 3)
Peak to Peak (differential) 300 1450 mV
dv/dt
Input Slew Rate - CLK_IN (Notes 3, 4)
Measured differentially 0.35 8 V/ns
I
IN
Input Leakage Current (Note 3)
V
IN
= V
DD
,
V
IN
= GND
−5 5
mA
d
tin
Input Duty Cycle (Note 3) Measurement from differential
waveform
45 55 %
J
DIFIn
Input Jitter - Cycle to Cycle (Note 3)
Differential Measurement 125 ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design and characterization, not tested in production.
4. Slew rate measured through ±75 mV window centered around differential zero.
5. Test configuration is; Rs = 27 W, 2 pF for 85 W transmission line.
NB3W800L
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6
Table 11. ELECTRICAL CHARACTERISTICS – Input/Supply/Common Parameters
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= 0°C * 70°C), See Test Loads for Loading Conditions. (Note 11)
Symbol
Parameter Conditions Min Typ Max Units
V
IH
Input High Voltage (Note 6) Single−ended inputs, except SMBus,
low threshold and tri−level inputs
2 V
DD
+ 0.3 V
V
IL
Input Low Voltage (Note 6) Single−ended inputs, except SMBus,
low threshold and tri−level inputs
GND − 0.3 0.8 V
I
IN
Input Current (Note 6)
Single−ended inputs,
V
IN
= GND, V
IN
= V
DD
−5 5
mA
I
INP
Single−ended inputs
V
IN
= 0 V; Inputs with internal pull−up
resistors V
IN
= V
DD
; Inputs with
internal pull−down resistors
−200 200
mA
F
ibyp
Input Frequency (Note 7)
V
DD
= 3.3 V, Bypass mode 33 150 MHz
F
ipll
V
DD
= 3.3 V, 100 MHz PLL mode 99 100.00 101 MHz
F
ipll
V
DD
= 3.3 V, 133.33 MHz PLL mode 132.33 133.33 134.33 MHz
L
pin
Pin Inductance (Note 6) 7 nH
C
IN
Capacitance (Note 6)
Logic Inputs, except CLK_IN 1.5 4.5 pF
C
INCLK_IN
CLK_INdifferential clock inputs (Note 9) 1.5 2.7 pF
C
OUT
Output pin capacitance 4.5 pF
f
MODIN
Input SS Modulation Frequency (Note 6) Allowable Frequency
(Triangular Modulation)
30 33 kHz
t
LATOE#
OE# Latency (Notes 6. 8) DIF start after OE# assertion
DIF stop after OE# deassertion
4 8 cycles
t
DRVPD
Tdrive_PD# (Notes 6, 8) DIF output enable after
PD# de−assertion
300
ms
t
F
Tfall (Notes 6, 7) Fall time of control inputs 10 ns
t
R
Trise (Notes 6, 7) Rise time of control inputs 10 ns
V
ILSMB
SMBus Input Low Voltage (Note 6) 0.8 V
V
IHSMB
SMBus Input High Voltage (Note 6) 2.1 V
DDSMB
V
V
OLSMB
SMBus Output Low Voltage (Note 6) @ I
PULLUP
0.4 V
I
PULLUP
SMBus Sink Current (Note 6) @ V
OL
4 mA
V
DDSMB
Nominal Bus Voltage (Note 6) 3 V to 5 V ±10% 2.7 5.0 V
t
RSMB
SCL/SDA Rise Time (Note 6)
(Max V
IL
- 0.15) to (Min V
IH
+ 0.15)
1000 ns
t
FSMB
SCL/SDA Fall Time (Note 6)
(Min V
IH
+ 0.15) to (Max V
IL
- 0.15)
300 ns
f
MAXSMB
SMBus Operating Frequency
(Notes 6, 10)
Maximum SMBus operating frequency 100 kHz
6. Guaranteed by design and characterization, not tested in production.
7. Control input must be monotonic from 20% to 80% of input swing.
8. Time from deassertion until outputs are >200 mV
9. CLK_IN input
10.The differential input clock must be running for the SMBus to be active
11. Test configuration is; Rs = 27 W, 2 pF for 85 W transmission line.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

NB3W800LMNG

Mfr. #:
Buy NB3W800LMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3 V 100/133 MHZ DIFFERE
Lifecycle:
New from this manufacturer.
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