OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

DS1391U-3+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
DS1390–DS1394
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
13
Maxim Integrated
Power Control
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the V
CC
level. The
device is fully accessible and data can be written and
read when V
CC
is greater than V
PF
. However, when
V
CC
falls below V
PF
, the internal clock registers are
blocked from any access. If V
PF
is less than V
BACKUP
,
the device power is switched from V
CC
to V
BACKUP
when V
CC
drops below V
PF
. If V
PF
is greater than
V
BACKUP
, the device power is switched from V
CC
to
V
BACKUP
when V
CC
drops below V
BACKUP
.
Timekeeping operation and register data are main-
tained from the V
BACKUP
source until V
CC
is returned to
nominal levels (Table 1). After V
CC
returns above V
PF
,
read and write access is allowed after RST goes high
(Figure 5).
Oscillator Circuit
All five devices use an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 2 specifies several crys-
tal parameters for the external crystal. If a crystal is
used with the specified characteristics, the startup time
is usually less than one second.
Clock Accuracy
The accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise
coupled into the oscillator circuit can result in the clock
running fast. Figure 7 shows a typical PC board layout
for isolation of the crystal and oscillator from noise.
Refer to Application Note 58:
Crystal Considerations
with Maxim Real-Time Clocks
for detailed information.
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency f
O
32.768 kHz
Series Resistance ESR 55 kΩ
Load Capacitance C
L
6pF
Table 2. Crystal Specifications*
*
The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Maxim Real-Time Clocks
for addi-
tional specifications.
SUPPLY
CONDITION
READ/WRITE
ACCESS)
POWERED BY
V
CC
< V
PF
,
V
CC
< V
BACKUP
No V
BACKUP
V
CC
< V
PF
,
V
CC
> V
BACKUP
No V
CC
V
CC
> V
PF
,
V
CC
< V
BACKUP
Yes V
CC
V
CC
> V
PF
,
V
CC
> V
BACKUP
Yes V
CC
Table 1. Power Control
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
GND
X2
X1
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
Figure 7. Layout Example
DS1390–DS1394
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
14
Maxim Integrated
Address Map
Table 3 shows the address map for the DS1390–
DS1393 RTC and RAM registers. The RTC registers are
located in address locations 00h to 0Fh in read mode,
and 80h to 8Fh in write mode. During a multibyte
access, when the address pointer reaches 0Fh, it
wraps around to location 00h. On the falling edge of the
CS pin (DS1390/DS1391/DS1394) or the rising edge of
CE (DS1392/DS1393), the current time is transferred to
a second set of registers. The time information is read
from these secondary registers, while the clock may
continue to run. This eliminates the need to re-read the
registers if the main registers update during a read. To
avoid rollover issues when writing to the time and date
registers, all registers should be written before the hun-
dredths-of-seconds registers reaches 99 (BCD).
When reading from the hundredths of seconds register,
there is a possibility that the data transfer happens at the
same time as an increment of the register. If this occurs,
the data in the buffer may be incorrect. The chances of
this happening is approximately 170ppb. There are two
ways to deal with this.
The first method is to synchronize enabling the device
(CE or CS) with the square wave or interrupt output
(DS1390–DS1394). Enabling the device, either after
detecting the falling edge of the interrupt output or the
rising edge of the square-wave output, ensures that the
two events are not simultaneous.
The second method is to read the hundredths of sec-
onds register until the data for two consecutive reads
match. With this method, the master must be able to
read the register at least twice within the 10ms update
period of the hundredths of seconds register.
Either of the described methods ensures that the data in
all the registers is correct. If the hundredths of seconds
register is not used, it is also possible for the same prob-
lem to occur when reading the seconds register. The
probability of an error is inversely proportional to the rate
of the register's update frequency in relation to the hun-
dredth of seconds register, so the error rate for the sec-
onds register would be approximately 1.7ppb. The same
methods used for the hundredth of seconds register
would be used for the seconds register.
WRITE
ADDRESS
READ
ADDRESS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
80h 00h Tenths of Seconds Hundredths of Seconds
Hundredths
of Seconds
0–99 BCD
81h 01h 0 10 Seconds Seconds Seconds 00–59 BCD
82h 02h 0 10 Minutes Minutes Minutes 00–59 BCD
AM/PM
83h 03h 0 12/24
10 Hour
10
Hour
Hour Hours
1–12 +AM/PM
00–23 BCD
84h 04h 0 0 0 0 0 Day Day 1–7 BCD
85h 05h 0 0 10 Date Date Date 01–31 BCD
86h 06h Century 0 0
10
Month
Month
Month/
Century
01–12 +
Century BCD
87h 07h 10 Year Year Year 00–99 BCD
88h 08h Tenths of Seconds Hundredths of Seconds
Alarm
Hundredths
of Seconds
0–99 BCD
89h 09h AM1 10 Seconds Seconds
Alarm
00–59 BCD
8Ah 0Ah AM2 10 Minutes Minutes
Alarm
00–59 BCD
Table 3. Address Map
DS1390–DS1394
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
15
Maxim Integrated
Hundredths-of-Seconds
Generator
The hundredths-of-seconds generator circuit shown in
the functional diagram is a state machine that divides
the incoming frequency (4096Hz) by 41 for 24 cycles
and 40 for one cycle. This produces a 100Hz output
that is slightly off during the short term, and is exactly
correct every 250ms. The divide ratio is given by:
Ratio = [41 x 24 + 40 x 1] / 25 = 40.96
Thus, the long-term average frequency output is
exactly the desired 100Hz.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. See Table 3 for the
RTC registers. The time and calendar are set or initial-
ized by writing the appropriate register bytes. The con-
tents of the time and calendar registers are in the bina-
ry-coded decimal (BCD) format. The day-of-week
register increments at midnight. Values that correspond
to the day-of-week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries
result in undefined operation. The DS1390–DS1393 can
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode-select
bit. When high, the 12-hour mode is selected. In the 12-
hour mode, bit 5 is the AM/PM bit with logic high being
PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20 to 23 hours). Changing the 12/24-hour mode-
select bit requires that the hours data be re-entered,
including the alarm register (if used). The century bit
(bit 7 of the month register) is toggled when the years
register overflows from 99 to 00.
WRITE
ADDRESS
READ
ADDRESS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
AM/PM
8Bh 0Bh AM3 12/24
10 Hour
10
Hour
Hour Alarm Hours
1–12 +
AM/PM
00–23 BCD
Day Alarm Day 1–7 BCD
8Ch 0Ch AM4 DY/DT 10 Date
Date Alarm Date 01–31 BCD
0 BBSQI RS2 RS1 INTCN 0 AIE DS1390/93/94
0 X X X X 0 X DS1391
8Dh 0Dh EOSC
0 BBSQI RS2 RS1 ESQW 0 AIE
Control
DS1392
8Eh 0Eh OSF 0 0 0 0 0 0 AF Status —
8Fh 0Fh TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
Trickle
Charger
—
Table 3. Address Map (continued)
Note: Unless otherwise specified, the state of the registers is not defined when power (V
CC
and V
BACKUP
) is first applied.
X = General-purpose read/write bit.
0 = Always reads as zero.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

DS1391U-3+

Mfr. #:
Buy DS1391U-3+
Manufacturer:
Maxim Integrated
Description:
Real Time Clock Low-V SPI/3-Wire With Trickle Charger
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet