DS1390–DS1394
Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
20
Maxim Integrated
SPI Serial-Data Bus
The DS1390/DS1391/DS1394 provide a 4-wire SPI seri-
al-data bus to communicate in systems with an SPI host
controller. The DS1390/DS1391 support SPI modes 1
and 3, while the DS1394 supports SPI modes 0 and 2.
Both devices support single-byte and multiple-byte
data transfers for maximum flexibility. The DIN and
DOUT pins are the serial-data input and output pins,
respectively. The CS input initiates and terminates a
data transfer. The SCLK pin synchronizes data move-
ment between the master (microcontroller) and the
slave (DS1390/DS1391) devices. The shift clock
(SCLK), which is generated by the microcontroller, is
active only during address and data transfer to any
device on the SPI bus. Input data (DIN) is latched on
the internal strobe edge and output data (DOUT) is
shifted out on the shift edge (Figure 9). There is one
clock for each bit transferred. Address and data bits
are transferred in groups of eight.
Address and data bytes are shifted MSB first into the
serial-data input (DIN) and out of the serial-data output
(DOUT). Any transfer requires the address of the byte
to specify a write or read, followed by one or more
bytes of data. Data is transferred out of the DOUT pin
for a read operation and into the DIN for a write opera-
tion (Figures 10 and 11).
The address byte is always the first byte entered after
CS is driven low. The most significant bit (W/R) of this
byte determines if a read or write takes place. If W/R is
0, one or more read cycles occur. If W/R is 1, one or
more write cycles occur.
Data transfers can occur one byte at a time or in multi-
ple-byte burst mode. After CS is driven low, an address
is written to the DS1390/DS1391/DS1394. After the
address, one or more data bytes can be written or
read. For a single-byte transfer, one byte is read or writ-
ten and then CS is driven high. For a multiple-byte
transfer, however, multiple bytes can be read or written
after the address has been written. Each read or write
cycle causes the RTC register address to automatically
increment. Incrementing continues until the device is
disabled. The address wraps to 00h after incrementing
to 0Fh (during a read) and wraps to 80h after incre-
menting to 8Fh (during a write). Note, however, that an
updated copy of the time is only loaded into the user-
accessible copy upon the falling edge of CS. Reading
the RTC registers in a continuous loop does not show
the time advancing.
