LTC3569
12
3569fe
For more information www.linear.com/LTC3569
operaTion
600mA; two independent regulators at 1.2A each, where
regulator 3 is placed in slave mode to regulator 2 and
regulator 1 operates independently; or one 1.8A regula-
tor and a second 600mA regulator, where regulator 2 is
placed in slave mode to regulator 1, and regulator 3 is
independent.
When regulator 2 is operating as a slave, pull pins EN2 and
FB2 up to SV
IN
to enable the slave power stage. Likewise
when regulator 3 is operated as a slave, pull pins EN3 and
FB3 up to SV
IN
to enable the slave power stage. If the EN
pin of the slave device is pulled low, then the slave power
stage is disabled and that SW pin is Hi-Z.
Shutdown and Soft-Start
The main control loop is shut down after pulling the ENx pin
to ground and waiting for the t
OFF
delay period to expire.
When in shutdown, but not in slave mode, a 2k resistor
to PGND discharges the output capacitor. When all three
regulators are turned off the LTC3569 enters low power
shutdown where all functions are disabled, and quiescent
current drops to below 1µA.
A soft-start is enabled when any buck is initially turned
on, or following a thermal shutdown. Soft-start ramps the
programmed internal reference at a rate of about 0.75V/ms.
The output voltage follows the internal reference voltage
ramp throughout the soft-start period. While in soft-start,
the LTC3569 is forced into pulse-skipping mode until the
PGOOD flag indicates that the output voltage is nearing
the programmed regulation voltage. Once the PGOOD flag
has tripped, if the MODE pin is high the regulator then
operates in Burst Mode, otherwise the LTC3569 continues
to operate in pulse-skipping mode.
Thermal Protection
If the die junction temperature exceeds 150°C, a thermal
shutdown circuit disables all functions in the LTC3569,
and the SW nodes will be pulled low with 2k pull-downs.
After the die temperature drops below 125°C the LTC3569
restarts without changing the programmed reference volt-
age DAC; but a soft-start is initiated upon exiting thermal
shutdown.
PGOOD Pin
The PGOOD pin is an open-drain output that indicates when
all of the enabled regulator’s output voltages have risen to
within 92% of their programmed levels. The three bucks
each have separate PGOOD comparators with hysteresis.
The PGOOD flag drops if one of the enabled regulator’s
output voltages drops below 88% of the programmed
level. Output voltage transient drops of duration less than
2µs are blanked and not reported at the PGOOD pin. The
PGOOD pin open-drain driver is disabled if PGOOD is
pulled up to a voltage above SV
IN
.
Programming the Reference
The full-scale reference voltage for each regulator is 0.8V.
The reference can be programmed in –25mV steps by
toggling the respective EN pin up to 15 times for a range
from 800mV down to 425mV. This is illustrated in Figure 3.
The EN pins require a minimum pulse width of 60ns, but
no more than 55µs, as the toggle counter times out after
the EN pin remains high for around 125µs (t
EN
). After the
t
EN
timeout, the counter state is latched and sent on to
the reference voltage DAC, and the counter is reset to full
scale. If the EN pin begins to toggle again, the counter
decrements on each falling edge. If the EN pin is toggled
more than 15 times, the counter remains fixed at the
lowest DAC reference level. To reprogram the DAC to full
scale, hold the EN pin low for 170µs (t
OFF
), turning off the
buck, and then pull EN high once. The buck then initiates
a soft-start as V
REF
ramps up to the full-scale value.
If the DAC is reprogrammed without forcing a shutdown,
the soft-start ramp is not engaged and the reference
steps to the new value. Avoid using the full-scale 0.8V
reference in programmable output voltage applications
if the application cannot tolerate the transition through
shutdown and soft-start when switching between different
reference levels.
