LTC3569
16
3569fe
For more information www.linear.com/LTC3569
applicaTions inForMaTion
Input/Output Capacitor Selection
Use low equivalent series resistance (ESR) ceramic
capacitors at the switching regulator outputs as well as
at the input supply pins. It is recommended to use only
X5R or X7R ceramic capacitors because they retain their
capacitance over wider voltage and temperature ranges
than other ceramic types.
For good transient response and stability the input and
output capacitors should retain at least 50% of rated ca-
pacitance value over temperature and bias voltage. Check
with capacitor data sheets to ensure that bias voltage and
temperature derating is taken into account when selecting
capacitors.
In continuous mode, the input supply current is a square
wave of duty cycle V
OUT
/V
IN
. The maximum input capacitor
ripple current is approximated by:
C
IN
required I
RMS
≈ I
OUT(MAX)
(V
OUT
(V
IN
–V
OUT
))
1/2
/V
IN
This formula’s maximum is approximately I
RMS
=
I
OUT(MAX)
/2.
In an output short-circuit situation, the input capacitor
ripple current is approximately:
C
IN
required I
RMS
≈ I
PK
/√3
Thus, the ripple current in an output short-circuit is about
2.5 times larger than for nominal operation. Take care
in selecting the input capacitor so as not to exceed the
capacitor manufacturers specification for self heating due
to the ripple current.
Two factors influence the selection of the output capacitor.
The first is load voltage droop, V
DROOP
, the second is the
output capacitor ESR effect on ripple voltage.
Load voltage droops on a load current step, I
OUT
, where
the output capacitor supports the output voltage for typi-
cally 2 to 3 clock cycles until the inductor current charges
up to the load step current level. A good estimate of output
capacitor value required to maintain a droop of less than
V
DROOP
is given by:
C
OUT
≈ 2.5I
OUT
/(f
CLK
•V
DROOP
)
The second factor that influences the selection of the output
capacitor is the effect of output capacitor ESR on the output
voltage ripple as a result of the inductor ripple current.
The amplitude of voltage ripple, V
OUT
, is determined by:
V
OUT
I
L
(ESR + 1/(8f
CLK
•C
OUT
))
Where I
L
is the ripple current in the inductor, and ESR
is the equivalent series resistance of the output capacitor.
Using ceramic capacitors, this voltage ripple is usually
negligible.
Table 2. Capacitors
VENDOR/PART NUMBER VALUE (µF)
Murata: GRM21BR71A106KE51 10
Murata: 06036D475KAT 4.7
TDK: C1608X5R0J106M
C1608X7R1C105K
10
1
Printed Circuit Board Layout Considerations
There are three main considerations to take into account
while designing a PCB layout for the LTC3569. The first
consideration is regarding switching noise coupling onto
the FB pin traces and the R
T
pin trace, or causing radiated
electromagnetic induction (EMI). The noise is mitigated
by placing the inductors and input decoupling capacitors
as close as possible to the LTC3569. Furthermore, careful
placement of a contiguous ground plane directly under
the high frequency switching node traces of the LTC3569
mitigates EMI; since high frequency eddy currents follow
the ground plane in loops. The larger the area of the cur-
rent return loops the larger EMI that is radiated. Placing
input decoupling capacitors close to the corresponding
PV
IN
/PGND pins directly reduces the area (and therefore
the inductance) of ground returns. Also, place a group of
vias directly under the grounded backside of the package
leading to an internal ground plane. Place the ground
plane on the second layer of the PCB to minimize parasitic
inductance.
LTC3569
17
3569fe
For more information www.linear.com/LTC3569
applicaTions inForMaTion
The second consideration is stray capacitance on the FB
pin traces and the R
T
pin trace to GND. This is taken into
account by cutting the ground plane beneath these traces.
However, wherever the ground plane is cut, add additional
decoupling capacitors across the break to provide a path
for high-frequency ground return currents to flow.
Finally, the third consideration is stray impedance between
the SW node and the inductor when operating with a slave
power stage. It is important to keep the stray inductance of
the slave power device to a minimum, by keeping the trace
from slave SW to the main SW as short as possible. This
requirement is necessary to ensure that the slave power
device’s share of the inductor current does not exceed that
of the master as well as to keep the current density in the
slave device under control. The inductor should be placed
close to the master SW pin to minimize stray impedance
and allow the master to control the inductor current.
Thermal Considerations
In the majority of applications, the LTC3569 does not dis-
sipate much heat due to its high efficiency. However, in
applications where the LTC3569 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, the LTC3569
will be turned off and 2k resistive pull-downs are tied to
all the SW nodes.
To prevent the LTC3569 from exceeding maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum junc-
tion temperature of the part. Temperature rise is:
t
RISE
= P
D
θ
JA
Where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= t
RISE
+ T
A
.
Where T
A
is the ambient temperature.
As an example, consider the case when the LTC3569 is
in dropout at an input voltage of 2.7V with load currents
of 1000mA, 500mA and 500mA for bucks 1, 2 and 3
respectively, at an ambient temperature of 85°C. From
the Typical Performance Characteristics, the R
DS(ON)
of
buck1 is 0.190Ω, and for buck2 and buck3 it is 0.265Ω.
Therefore, power dissipated by the LTC3569 is:
P
D
= I
1
2
R
DS(ON)1
+ I
2
2
R
DS(ON)2
+ I
3
2
R
DS(ON)3
= 190mV + 66.25mW + 66.25mV
= 322.5mW
At 85°C ambient the junction temperature is:
T
J
= 322.5mW68°C/W + 85°C = 106.9°C.
This junction temperature is below the absolute maximum
junction temperature of 125°C.
Design Example 1: 2.5V, 1.8V and 1.2V From a
Li-Ion Battery
As a design example, consider using the LTC3569 in a
portable application with a Li-Ion battery source. The bat-
tery provides an SV
IN
from 2.9V to 4.2V. The loads require
2.5V, 1.8V and 1.2V with current requirements of up to
800mA, 400mA and 400mA respectively when active. The
first load, with the 2.5V rail has no standby requirements,
however loads 2 and 3 each require a current of 1mA in
standby. Since two of the loads require low current opera-
tion, Burst Mode operation is selected. With V
IN(MAX)
at
4.2V and V
OUT(MIN)
= 1.2V, the maximum clock frequency
is 3.57MHz based on minimum on-time requirements.
To simplify the board layout, the fixed 2.25MHz internal
frequency is selected.
LTC3569
18
3569fe
For more information www.linear.com/LTC3569
Selecting The Inductors
Calculating the inductor values for 30% ripple current at
maximum SV
IN
:
L1 = 2.5V/(2.25MHz240mA)•(1–2.5V/4.2V)= 1.9µH
L2 = 1.8V/(2.25MHz120mA)•(1–1.8V/4.2V)= 3.8µH
L3 = 1.2V/(2.25MHz120mA)•(1–1.2V/4.2V)= 3.1µH
Choosing a vendors closest values gives L1 = 2.2µH, L2
= L3 = 3.3µH. These values result in the maximum ripple
currents of:
I
L1
= 2.5V/(2.25MHz•2.2µH)•(1–2.5V/4.2V) = 204mA
I
L2
= 1.8V/(2.25MHz•3.3µH)•(1–1.8V/4.2V) = 139mA
I
L3
= 1.2V/(2.25MHz•3.3µH)•(1–1.2V/4.2V) = 115mA
Selecting The Output Capacitors
The value of the output capacitors are calculated based
on a 5% load droop for maximum load current step. The
output droop is usually about 2.5 times the linear drop
of the first cycle and is estimated based on the following
formula:
C
OUT
= 2.5I
OUT(MAX)
/(f
CLK
•V
DROOP
)
The output capacitor values are calculated as:
C
OUT1
= 2.5800mA/(2.25MHz125mV) = 7.1µF
C
OUT2
= 2.5400mA/(2.25MHz90mV) = 4.9µF
C
OUT3
= 2.5400mA/(2.25MHz60mV) = 7.4µF
Choosing the closest standard values gives, C
OUT1
= 10µF,
C
OUT2
= 4.7µF and C
OUT3
= 10µF.
A 22µF input capacitor is selected since the Li-Ion battery
has sufficiently low output impedance.
Setting The Output Voltages
Without toggling the EN pins the LTC3569 develops a 0.8V
reference voltage for each of the feedback pins. The output
voltages are set by a resistive divider as follows:
V
OUT
= 0.8(1 + R1/R2)
The resistors in Figure 5 are selected as the nearest 1%
standard resistor values. To improve frequency response
feedforward capacitors of 10pF and 20pF are used.
applicaTions inForMaTion
Figure 5. Triple Buck DC/DC Regulators: 800mA, 400mA, 400mA
Design Example 1: Burst Mode Operation
3569 F05a
SV
IN
PV
IN
SW1
PGNDSGND
SW2
SW3
PGOOD
FB1
EN1
EN2
EN3
R
T
MODE
FB2
FB3
22µF
V
IN
2.9V TO 4.2V
L1
2.2µH*
C
OUT1
10µF
10pF
20pF
C
OUT2
4.7µF
L2
3.3µH**
243k
115k
187k
150k
OUT1
2.5V AT 800mA
OUT2
1.8V AT 400mA
20pF
C
OUT3
10µF
L3
3.3µH**
187k
374k
OUT3
1.2V AT 400mA
LTC3569
470k
* WURTH 7447745022
** WURTH 7447745033
I
LOAD
(mA)
EFFICIENCY (%)
3569 F05b
100
90
80
70
60
50
0.1 1 1000 1000010010
BUCK1 = 2.5V
BUCK2 = 1.8V
BUCK3 = 1.2V
V
IN
= 2.9V TO 4.2V

LTC3569EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Programmable 1.2A and 2X600mA, Triple Buck Regulator
Lifecycle:
New from this manufacturer.
Delivery:
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