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TEA1752LT/N1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
TEA1752LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 15 November 2012 10 of 33
NXP Semiconductors
TEA1752LT
HV start-up flyback controller with integrated PFC controller
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is
limited to f
sw(PFC)max
. If the frequency for quasi-resonant operation is above the f
sw(PFC)max
limit, the system switches over to DCM. The PFC MOSFET is only switched on at a
minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The equation for the transfer function of a power factor corrector contains the square of
the mains input voltage. In a typical application this results in a low bandwidth for low
mains input voltages and a high bandwidth for high mains input voltages.
To compensate for the mains input voltage influence, the TEA1752LT contains a
correction circuit. The average input voltage is measured using the VINSENSE pin and
the information is fed to an internal compensation circuit. Using this compensation, it is
possible to keep the regulation loop bandwidth constant over the mains input range. This
yields a fast transient response on load steps, while still complying with class-D MHR
requirements.
In a typical application, a resistor and two capacitors on the PFCCOMP pin set the
bandwidth of the regulation loop.
7.2.5 Soft-start-up (PFCSENSE pin)
To prevent audible transformer noise at start-up or during hiccup, the soft-start function
slowly increases the transformer peak current. This increase is achieved by inserting R
SS1
and C
SS1
between the PFCSENSE pin and current sense resistor R
SENSE1
. An internal
current source charges the capacitor to:
(1)
The voltage is limited to V
start(soft)PFC
.
The start level and the time constant of the increasing primary current level are adjusted
externally by changing the values of R
SS1
and C
SS1
.
(2)
The charging current I
start(soft)PFC
flows as long as V
PFCSENSE
is below 0.5 V. If V
PFCSENSE
exceeds 0.5 V, the soft-start current source starts limiting current I
start(soft)PFC
. When the
PFC starts switching, the I
start(soft)PFC
current source is switched off (see Figure 5).
soft s– tart 3 R
SS1
C
SS1
=
TEA1752LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 15 November 2012 11 of 33
NXP Semiconductors
TEA1752LT
HV start-up flyback controller with integrated PFC controller
7.2.6 Low-power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency reduction mode. When the maximum switching
frequency of the flyback drops below 48 kHz, the power factor correction circuit is
switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay
switching off (see Section 7.2.7
).
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.5 V and a maximum voltage of 3.9 V. The lower clamp voltage limits the maximum
power that is delivered when the PFC is switched on again. The upper clamp voltage
ensures that the PFC returns to its normal regulation point in a limited time.
When the flyback converter frequency exceeds 86 kHz, the power factor correction circuit
restores normal operation.
7.2.7 PFC off delay (pin PFCTIMER)
When the flyback converter maximum frequency drops below 48 kHz, the PFC is switched
off. The IC then outputs a 10 A current to the PFCTIMER pin. When the voltage on the
PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.
When the flyback converter frequency exceeds 86 kHz, a switch discharges the
PFCTIMER pin capacitor. When the voltage on the PFCTIMER pin drops below 1.27 V,
the PFC is switched on (see Figure 6
).
Fig 5. Soft start-up of PFC
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Fig 6. PFC start/stop via PPFCTIMER pin
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TEA1752LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 15 November 2012 12 of 33
NXP Semiconductors
TEA1752LT
HV start-up flyback controller with integrated PFC controller
7.2.8 Dual boost PFC
The mains input voltage modulates the PFC output voltage. The mains input voltage is
measured using the VINSENSE pin. If the voltage on the VINSENSE pin drops below
2.2 V, the current is sourced from the VOSENSE pin. To ensure the stable switch-over, a
200 mV transition region is inserted around the 2.2 V (see Figure 7
).
At low VINSENSE input voltages, the output current is 15 A. This output current, in
combination with the resistors on the VOSENSE pin, sets the lower PFC output voltage
level at low mains voltages. At high mains input voltages, the current switches to zero.
The PFC output voltage is then at its maximum. As this current is zero in this situation, it
does not affect the accuracy of the PFC output voltage.
To ensure proper switch-off, the VOSENSE current switches to its maximum value of
15 A when the voltage on the VOSENSE pin drops below 2.1 V.
7.2.9 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor, R
SENSE1
, on the source of the external MOSFET. The voltage is
measured using the PFCSENSE pin.
7.2.10 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, the voltage on the
VINSENSE pin is continuously sensed. When the voltage on this pin drops below the
V
stop(VINSENSE)
level, switching of the PFC is stopped.
The voltage on the VINSENSE pin is clamped to a minimum value, V
start(VINSENSE)
V
pu(VINSENSE)
. This voltage clamping provides for a fast restart when the mains input
voltage is restored after a mains dropout
7.2.11 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage
protection circuit is built in.
When the voltage on the VOSENSE pin exceeds the V
OVP(VOSENSE)
level, switching of the
power factor correction circuit is stopped. Switching of the PFC recommences when the
VOSENSE pin voltage drops below the V
OVP(VOSENSE)
level again.
Fig 7. Voltage to current transfer function for dual boost PFC
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

TEA1752LT/N1,518

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Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters IC CTLR SMPS SW MODE
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