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TEA1752LT/N1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
TEA1752LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 15 November 2012 25 of 33
NXP Semiconductors
TEA1752LT
HV start-up flyback controller with integrated PFC controller
I
O(FBCTRL)
output current on the FBCTRL
pin
V
FBCTRL
=0V 1.4 1.19 0.93 mA
V
FBCTRL
=2V 0.6 0.5 0.4 mA
I
to(FBCTRL)
time-out current on the
FBCTRL pin
V
FBCTRL
=2.6V 36 30 24 A
V
FBCTRL
=4.1V 34.5 28.5 22.5 A
Valley switching flyback (HV pin)
(V/t)
vrec(fb)
flyback valley recognition
voltage change with time
75 - +75 V/s
t
d(vrec-swon)
valley recognition to switch on
delay time
[4]
-150-ns
Soft-start flyback (FBSENSE pin)
I
start(soft)fb
flyback soft-start current 75 60 45 A
V
start(soft)fb
flyback soft-start voltage enable voltage 0.55 0.63 0.70 V
Overcurrent protection flyback (FBSENSE pin)
V
sense(fb)max
maximum flyback sense
voltage
V/t=50mV/s 0.61 0.65 0.69 V
V/t=200mV/s 0.64 0.68 0.72 V
V
sense(fb)min
minimum flyback sense voltage V/t=50mV/s 0.305 0.325 0.345 V
t
leb(fb)
flyback leading edge blanking
time
255 305 355 ns
I
adj(FBSENSE)
adjust current on the
FBSENSE pin
3.2 3 2.8 A
Overpower protection flyback (FBSENSE pin)
V
sense(fb)max
maximum flyback sense
voltage
V/t=50mV/s
I
FBAUX
=80A 0.61 0.65 0.69 V
I
FBAUX
=120A 0.57 0.62 0.67 V
I
FBAUX
=240A 0.47 0.52 0.57 V
I
FBAUX
=360A 0.41 0.46 0.51 V
Driver (FBDRIVER pin)
I
src(FBDRIVER)
source current on the
FBDRIVER pin
V
FBDRIVER
=2V - 0.5 - A
I
sink(FBDRIVER)
sink current on the FBDRIVER
pin
V
FBDRIVER
=2V - 0.7 - A
V
FBDRIVER
=10V -1.2-A
V
O(FBDRIVER)(max)
maximum output voltage on the
FBDRIVER pin
9.5 10.8 12 V
LATCH input (LATCH pin)
V
prot(LATCH)
protection voltage on the
LATCH pin
1.23 1.25 1.27 V
I
O(LATCH)
output current on the LATCH
pin
V
prot(LATCH)
<V
LATCH
<V
oc(LATCH)
85 80 75 A
V
en(LATCH)
enable voltage on the LATCH
pin
at start-up 1.30 1.35 1.40 V
V
hys(LATCH)
hysteresis voltage on the
LATCH pin
V
en(LATCH)
V
prot(LATCH)
80 100 140 mV
Table 5. Characteristics
…continued
T
amb
=25
C; V
CC
= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA1752LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 15 November 2012 26 of 33
NXP Semiconductors
TEA1752LT
HV start-up flyback controller with integrated PFC controller
[1] For a typical application with a compensation network on pin PFCCOMP, like the example in Figure 3.
[2] Minimum required voltage change time for valley recognition on pin PFCAUX.
[3] Minimum time required between demagnetization detection and V/t = 0 on pin PFCAUX.
[4] Guaranteed by design.
V
oc(LATCH)
open-circuit voltage on the
LATCH pin
2.65 2.9 3.15 V
Temperature protection
T
pl(IC)
IC protection level temperature 130 140 150 C
T
pl(IC)hys
hysteresis of IC protection level
temperature
-10-C
Table 5. Characteristics …continued
T
amb
=25
C; V
CC
= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into
the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA1752LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 15 November 2012 27 of 33
NXP Semiconductors
TEA1752LT
HV start-up flyback controller with integrated PFC controller
11. Application information
A power supply with the TEA1752LT consists of a power factor correction circuit and a
flyback converter (see Figure 17
).
Capacitor C
VCC
buffers the IC supply voltage. The IC is powered using the high voltage
rectified mains during start-up and the auxiliary winding of the flyback converter during
operation. Sense resistors R
SENSE1
and R
SENSE2
convert the current through the
MOSFETs S1 and S2 into a voltage at the PFCSENSE and FBSENSE pins. The values of
R
SENSE1
and R
SENSE2
define the maximum primary peak current in MOSFETs S1 and S2.
In the example given, the LATCH pin is connected to a Negative Temperature Coefficient
(NTC) resistor. The protection is activated when the resistance drops below a value
calculated as follows:
(8)
A capacitor C
TIMEOUT
is connected to the FBCTRL pin. R
LOOP
is added so that the
time-out capacitor does not interfere with the normal regulation loop.
R
S1
and R
S2
are added to prevent the soft-start capacitors from being charged during
normal operation due to negative voltage spikes across the sense resistors.
Resistor R
AUX1
is added to protect the IC from damage during lightning events.
RS3 and RCOMP are added to compensate for input voltage variations. The (stray)
capacitance on the drain node of MOSFET S3 affects the frequency reduction slope and
therefore the PFC switch-on and switch-off levels. Choosing the proper values for RS3
and RCOMP results in an input voltage independent PFC switch-on and switch-off power
level.
V
prot LATCH
I
OLATCH
-------------------------------
15.6 k=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

TEA1752LT/N1,518

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Buy TEA1752LT/N1,518
Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters IC CTLR SMPS SW MODE
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