Data Sheet HMC903-Die
Rev. A | Page 9 of 13
APPLICATIONS INFORMATION
Figure 25 shows the basic connections for operating the
HMC903-Die in self biased operation. Both the RFIN and the
RFOUT ports have on-chip dc block capacitors, eliminating the
need for external ac coupling capacitors.
The HMC903-Die has V
GG
1 and V
GG
2 optional gate bias pads.
When these pads are left open, the amplifier runs in self biased
operation with typical I
DQ
= 90 mA when V
DD
= 3.5 V. When
using the optional V
GG
1 and V
GG
2 gate bias pads, use the
recommended bias sequencing to prevent damage to the
amplifier.
The recommended bias sequence during power-up is as follows:
1. Connect to GND.
2. Set V
GG
1 and V
GG
2 to −2 V.
3. Set V
DD
1 and V
DD
2 to +3.5 V.
4. Increase V
GG
1 and V
GG
2 to achieve a typical I
DQ
= 90 mA.
5. Apply the RF signal.
The recommended bias sequence during power-down is as follows:
1. Turn off the RF signal.
2. Decrease V
GG
1 and V
GG
2 to −2 V to achieve a typical I
DQ
=
0 mA.
3. Decrease V
DD
1 and V
DD
2 to 0 V.
4. Increase V
GG
1 and V
GG
2 to 0 V.
The bias conditions previously listed (V
DD
1 and V
DD
2 = 3.5 V
and I
DQ
= 90 mA) are the recommended operating points to
achieve optimum performance. The data used in this data sheet
is taken with the recommended bias conditions listed in the
Electrical Specifications section. If the HMC903-Die is used
with different bias conditions than what is recommended, a
different performance than what is shown in the Typical
Performance Characteristics section can result. Decreasing the
V
DD
level has a negligible effect on gain and NF performance,
but reduces P1dB. This behavior is shown in Figure 18. For
applications where the P1dB requirement is not stringent, the
HMC903-Die can be down biased to reduce power
consumption.
