[AK4117]
MS0157-E-04 2010/08
- 14 -
■ System Reset and Power-Down
The AK4117 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down
mode activated by the PWN bit. The RSTN bit initializes the internal registers and timing. The AK4117 should be reset
once at power-up by bringing PDN pin = “L”.
PDN Pin:
All analog and digital circuits are placed in power-down and reset modes by bringing PDN= “L”. All the registers
are initialized and clocks are stopped. Read/write operations to the registers are disabled.
RSTN Bit (Address 00H; D0):
All the registers except RSTN, PWN, XTL1-0 and EXCK are initialized by bringing RSTN bit = “0”. The internal
timings are also initialized. When RSTN bit= “0”, clocks are output, but SDTO is “L”. All register writes except
RSTN, PWN, XTL1-0 and EXCK are disabled. Reading from the registers is enabled.
PWN Bit (Address 00H; D1):
Clock recovery mode is initialized by bringing PWN bit = “0”. Clocks from the PLL are stopped while the X’tal
clocks continue to be output. Unlike the PDN pin operation described above, internal registers and mode settings
are not initialized. Read/write operations to the registers are enabled.
■ Biphase Input
Two receiver inputs (RX0 and RX1) are available. Each input includes an amplifier for unbalance loads that can accept
350mVpp or greater signal. The IPS bit selects the receiver channel (
Table 7). When the UOUTE bit = “1”, the U bit
(user data) can be output from the UOUT pin.
IPS INPUT Data
0 RX0 Default
1 RX1
Table 7. Recovery Data Select
UOUT
LRCK
(except I
2
S)
L0 R0 L1
R31L31 L32R191
SDTO
L191 R191 L30
L31
R30
L0
R190
LRCK
(I
2
S)
Figure 11. UOUT output timing
