[AK4117]
MS0157-E-04 2010/08
- 19 -
INT0/1 pin ="H"
No
Yes
Yes
Initialize
PDN pin ="L" to "H"
Read 05H
Mute DAC output
Read 05H
No
(Each Error Handling)
Read 05H
(Resets registers)
INT0/1 pin ="H"
Release
Muting
Figure 18. Interrupt Handling Sequence Example 1
[AK4117]
MS0157-E-04 2010/08
- 20 -
INT1 pin ="H"
No
Yes
Initialize
PDN pin ="L" to "H"
Read 05H
Read 05H
and
Detect QSUB= “1”
No
(Read Q-buffer)
New data
is valid
INT1 pin ="L"
QCRC = “0”
Yes
Yes
New data
is invalid
No
Figure 19. Interrupt Handling Sequence Example (for Q/CINT)
[AK4117]
MS0157-E-04 2010/08
- 21 -
Audio Serial Interface Format
The DIF2-0 bits can select six serial data formats as shown in Table 9. In all formats, the serial data is MSB-first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on the rising edge of
BICK. BICK outputs 64fs clock. When the SDTO format is equal or less than 20 bits (Mode 0-2), LSBs in the sub-frame
are truncated. In Modes 3-7, the last four LSBs are auxiliary data (see
Figure 20).
When a Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, the AK4117 continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When an Unlock Error occurs, the AK4117
outputs “0” from SDTO. When using the DAUX pin, the data is transformed and output from SDTO. The DAUX pin is
used in Clock Operation Modes 1, 3 and in the unlock state of Mode 2. The input data format to DAUX should be
left-justified except in Mode 5. In Mode 5, both the input data format of DAUX and the output data format of SDTO are
I
2
S.
0 3 4 7 8 11 12 27 28 29 30 31
preamble Aux.
LSB MSB
VUC P
sub-frame of IEC60958
023
AK4117 Audio Data (MSB First)
LSBMSB
Figure 20. Bit configuration
Mode DIF2 DIF1 DIF0 DAUX SDTO LRCK
0 0 0 0 24bit, Left justified 16bit, Right justified H/L
1 0 0 1 24bit, Left justified 18bit, Right justified H/L
2 0 1 0 24bit, Left justified 20bit, Right justified H/L
3 0 1 1 24bit, Left justified 24bit, Right justified H/L
4 1 0 0 24bit, Left justified 24bit, Left justified H/L
Default
5 1 0 1 24bit, I
2
S 24bit, I
2
S L/H
6 1 1 0
7 1 1 1
Reserved
Table 9. Audio data format

AK4117VF

Mfr. #:
Manufacturer:
Description:
IC RCVR DGTL AUD 24VSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet