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307G-03LF

P1-P3P4-P6P7-P9P10-P12P13-P14
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 10
ICS307-03 REV L 032911
Programming Interface
The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time after
power is properly applied. If V or R values are changed, the frequency will transition smoothly to the new value
without glitches or short cycles. However, changing any divider or mux in the output signal path may generate a
glitch.
The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data bit value in
the rising edge. It latches the most recently shifted 132 bit values into the control register of device whenever CS is
high. Care must be taken to ensure that CS is always low until the system is ready to load in a new register value
and that SCLK is never toggled high when CS is high.
The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit 112 held
low) with the waveform and timing shown below:.
Figure 2: ICS307-03 Programming Timing Diagram
Table 8: AC Parameters for Programming the ICS307-03
Programming with VersaClock Software
The VersaClock II Software not only generates the programming word for the user, it can also be used to program the device
via the host computer’s parallel port. Demonstration boards are available from IDT that allows the VersaClock II S/W to
directly connect the ICS307-03 to a Windows based PC’s DB-25 parallel port connector and programmed simply by pressing
the “Program Part” button.
Parameter Condition Min. Max. Units
t
SETUP
Setup time 2.5 ns
t
HOLD
Hold time after SCLK 2.5 ns
t
W
Data wait time 2.5 ns
t
S
Strobe pulse width 10 ns
SCLK Frequency 200 MHz
128129130131 10
t
hold
t
setup
2
SCLK
CS
t
s
t
w
DIN
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 11
ICS307-03 REV L 032911
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS307-03. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability.
Electrical parameters are guaranteed only over the recommended operating temperature range.
Recommended Operating Conditions
DC Electrical Characteristics
VDD=3.3 V ±0.3 V, Ambient temperature 0 to +70° C, unless stated otherwise
Item Rating
Supply Voltage, VDD 5 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Storage Temperature -65 to +150° C
Soldering Temperature 260° C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature 0 +70 ° C
Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.0 3.6 V
Input High Voltage V
IH
2V
Input Low Voltage V
IL
0.8 V
Output High Voltage V
OH
I
OH
= -4 mA 2.4 V
Output Low Voltage V
OL
I
OL
= 4 mA 0.4 V
Output High Voltage,
CMOS level
V
OH
I
OH
= -6.5 mA VDD-0.4 V
Tri-state Output Leakage 1 µA
Operating Supply Current IDD 27 MHz crystal
No load, 100 MHz out,
all outputs enabled
24 mA
Short Circuit Current CLK outputs ±60 mA
Input Capacitance C
IN
4pF
On-Chip Pull-up Resistor R
PU
240 kΩ
On-Chip Pull-down
Resistor
R
PD
100 kΩ
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 12
ICS307-03 REV L 032911
AC Electrical Characteristics
VDD = 3.3 V ±0.3 V, Ambient Temperature 0 to +70° C, unless stated otherwise
Note 1: Measured with 15 pF load.
Note 2: Jitter performance will change depending on configuration settings.
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency F
IN
Fundamental crystal 3 27 MHz
Clock 0.1 300 MHz
Clock Output Frequency F
OUT
5 pF load 0.0002 270 MHz
15 pF load 0.0002 200 MHz
Output Clock Rise/Fall Time t
R,
t
F
20 to 80% (5 pF load) 1.5 ns
Output Clock Duty Cycle Output Divides <> 3 45 49-51 55 %
Output Divide = 3 40 60 %
Frequency Transition time STROBE high to CLK
out
310ms
One Sigma Clock Period Jitter Note 2 50 ps
Maximum Absolute Jitter t
ja
Deviation from mean,
Note 2
±120 ps
VCO Frequency VCO
F
100 730 MHz
Divider 1 Input Output divider 1 = 2
(5 pF load)
540 MHz
Output divider 1 = 2
(15 pF load)
400 MHz
Output divider 1 = 3
(5 pF load)
720 MHz
Output divider 1 = 3
(15 pF load)
600 MHz
Output divider 1 = 38
~ 1029
570 MHz
All other Output
Divider 1 values
730 MHz
Divider 2 and 3 Inputs Output divider 2, 3 = 2
(5 pF load)
540 MHz
Output divider 2, 3 = 2
(15 pF load)
400 MHz
Output divider 2, 3=12 440 MHz
Output divider 2, 3 =
16, 24, 28 and 32
500 MHz
All other Output
Divider 2 & 3 values
730 MHz
P1-P3P4-P6P7-P9P10-P12P13-P14

307G-03LF

Mfr. #:
Buy 307G-03LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution SERIAL PROGRAMMABLE CLOCK SOURCE
Lifecycle:
New from this manufacturer.
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