ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 5
ICS307-03 REV L 032911
Table 5. Output Divider for Output 1
Divide
Value 109 108 107 106 105 104 103
Bits
102 101 100 99 98 97 96 95 Rule
2 XXXXXXX X XXX0000
3 XXXXXXX X XXX0001
4 XXXXXXX X XXX1000
5 XXXXXXX X XXXX010
6 XXXXXXX X XXX1001
7 XXXXXXX X XX00011
8 X X X X X X X 1 1 1 0 1 1 0 0 apply Rule from Divide Values 14-37
9 XXXXXXX X XX01011
10 X X X X X X X 1 1 0 1 1 1 0 0
apply Rule from Divide Values 14-37
11 XXXXXXX X XX10011
12 X X X X X X X 1 1 0 0 1 1 0 0
apply Rule from Divide Values 14-37
13 XXXXXXX X XX11011
14 X X X X X X X 1 0 1 1 1 1 0 0 subtract 6 from the desired divide
value, convert to binary, invert, and
apply to bits 102..98
set bits [97..95] = 100
15 X X X X X X X 1 0 1 1 0 1 0 0
36 X X X X X X X 0 0 0 0 1 1 0 0
37 X X X X X X X 0 0 0 0 0 1 0 0
38 0000100 0 0001101output divide =
((([109..101]+3)*2)+[98
])*2^[100..99]
set bits [95..97] = 101
39 0000100 0 0000101
…
(increments of 1) set bits [95..97] = 101
†
1029 1111111 1 1000101(
†
this Rule applies to Divide Values
38-8232)
1030 0111111 1 0010101
1032 0111111 1 1011101
…
(increments of 2)
2056 1111111 1 1011101
2058 1111111 1 1010101
2060 0111111 1 0100101
2064 0111111 1 1101101
…
(increments of 4)
4112 1111111 1 1101101
4116 1111111 1 1100101
4120 0111111 1 0110101
4128 0111111 1 1111101
…
(increments of 8)
8224 1111111 1 1111101
8232 1111111 1 1110101
