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307G-03LF

P1-P3P4-P6P7-P9P10-P12P13-P14
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 7
ICS307-03 REV L 032911
Table 8. Miscellaneous Control Bits
External Components
The ICS307-03 requires a minimum number of external components for proper operation.
Decoupling Capacitors
TheICS307-03 requires 0.01μF decoupling capacitors to be connected between each VDD pin and the Ground Plane. The
0.01μF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead inductance.
Output Termination
The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation with single
ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50 Ohm transmission
line without the need for any series resistors.
Crystal Selection
A parallel resonant, fundamental mode crystal with a load
(correlation) capacitance of 12 pF should be used. For
crystals with a specified load capacitance greater than 12
pF, additional crystal capacitors may be connected from
each of the pins X1 and X2 to ground as shown in the Block
Diagram on page 1. The value (in pF) of these crystal caps
should be = (C
L
-12)*2, where C
L
is the crystal load
capacitance in pF.
For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.
Initial Output Frequency
ICS307-03 on-chip registers are initially configured to
provide a 1x output clock on the CLK1 output, and 0.5x clock
on CLK2 and CLK3. The output frequency will be the same
as the input clock or crystal for input frequencies from 10 -
50 MHz. This is useful when the ICS307-03 needs to
provide an initial system clock at power-up.
Bit Function
24~88 Reserved—set to 0
110 OE1—set to 1 to enable CLK1
111 OE2—set to 1 to enable CLK2
112 1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO
122 Crystal Input = 1, Clock Input = 0
123 Selects source for CLK2 (see block diagram)
124 Selects source for CLK3 (see block diagram)
125 Reserved—set to 0
126 Reserved—set to 0
129 OE3—set to 1 to enable CLK3
130 Reserved—set to 0
131 Reserved—set to 0
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 8
ICS307-03 REV L 032911
Determining and Controlling the Output Frequency with VersaClock
TM
II
The ICS307-03 is directly supported by the IDT provided
software called VersaClock II. Complete programming
words for this device can be calculated on any Windows PC
by running the VersaClock II software and simple inputting
desired input and output frequencies. Once the software
generates an appropriate programming word, it may then be
either copied to the Windows clipboard or even directly
programmed into the ICS307-03 via the host computers
parallel port.
For more information on VersaClock II, please visit
www.idt.com.
Manually Determining the Output Frequency
The user has full control over the desired output frequency
as long as it is operated within the limits shown in the AC
Electrical Characteristics.
The output of the ICS307-03 can be determined by the
following equation:
Where:
VCO Divider (V) = 12 to 2055
Reference Divider Word (R) = 1 to 2055
Output Divider = values in tables 5, 6, 7
Also, the following operating ranges should be observed.
To determine the best combination of VCO, reference, and
output dividers, please use the VersaClock II software
mentioned above.
CLK1Frequency InputFrequency
V
ROD⋅
--------------------
⋅=
VCOmin InputFrequency
V
R
---- VCOmaxfreq<⋅<
20kHz
Input Frequency
R
-------------------------------------------100MHz<<
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE SER PROG CLOCK SYNTHESIZER
IDT®
SERIALLY PROGRAMMABLE CLOCK SOURCE 9
ICS307-03 REV L 032911
Setting the PLL Loop Response
The PLL loop response is determined both by fixed device
characteristics and by other characterizes set by the user.
This includes the values of R
S
and C
S
as shown in the PLL
Components figure on this page.
The PLL loop bandwidth is approximated by:
Where:
R
S
= Value of resistor R
S
in loop filter in Ohms
I
CP
= Charge pump current in amps
K
O
= VCO Gain in Hz/V
FV Divider = 12 to 2055
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by C
P
. It does, however, provide a useful
approximation of filter performance.
To prevent jitter due to modulation of the PLL by the phase
detector frequency, the following general rule should be
observed:
.
The PLL loop damping factor is determined by:
Where:
C
S
= Value of capacitor C
S
in loop filter in Farads
= 300e
-12
in Farads
Default Register Values
At power-up, the registers are set to:
ref divide = 5
VCO divide = 50
output divide = 10 (CLK1)
output divide = 2 (CLK2)
output divide = 2 (CLK3)
bit 123, 124 = 1
ICP = 3.75 µA
R = 16k
Default programming word is:
0x31FFDFFEE3BFFFFFFFFFFFFFFFF055FF2
NBW(PLL)
R
S
I
CP
× K
O
×
2π FV Divider×
------------------------------------------=
NBW(VCO PLL)
f(Phase Detector)
10
---------------------------------------
≤
P1-P3P4-P6P7-P9P10-P12P13-P14

307G-03LF

Mfr. #:
Buy 307G-03LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution SERIAL PROGRAMMABLE CLOCK SOURCE
Lifecycle:
New from this manufacturer.
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