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LTC1098LCS8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LTC1096/LTC1096L
LTC1098/LTC1098L
10
10968fc
TYPICAL PERFORMANCE CHARACTERISTICS
Wake-Up Time vs Supply Voltage
Minimum Wake-Up Time
vs Source Resistance
Input Channel Leakage Current
vs Temperature
Minimum Clock Frequency for
0.1LSB Error
†
vs Temperature ENOBs vs Frequency FFT Plot
Maximum Clock Frequency vs
Source Resistance
Maximum Clock Frequency vs
Supply Voltage
Digital Input Logic Threshold
vs Supply Voltage
* Maximum CLK frequency represents the clock frequency at which a 0.1LSB shift in the error at any code
transition from its 0.75MHz value is fi rst detected.
†
As the CLK frequency is decreased from 500kHz, minimum CLK frequency (Δerror ≤ 0.1LSB) represents
the frequency at which a 0.1LSB shift in any code transition from its 500kHz value is fi rst detected.
R
SOURCE
–
(kΩ)
1
0
MAXIMUM CLOCK FREQUENCY* (MHz)
0.25
0.50
1
10 100
10968 G10
0.75
+ INPUT
– INPUT
R
SOURCE
–
V
IN
T
A
= 25°C
V
CC
= V
REF
= 5V
SUPPLY VOLTAGE (V)
0
0
MAXIMUM CLOCK FREQUENCY (MHz)
0.25
0.5
0.75
1.0
1.25
1.5
2468
10968 G11
10
T
A
= 25°C
V
REF
= 2.5V
SUPPLY VOLTAGE, V
CC
(V)
0
LOGIC THRESH0LD (V)
3
4
5
8
10968 G12
2
1
0
2
4
6
10
T
A
= 25°C
SUPPLY VOLTAGE, V
CC
(V)
0
WAKE-UP TIME (μs)
3
4
8
10968 G13
2
1
0
2
4
6
10
T
A
= 25°C
V
REF
= 2.5V
R
SOURCE
(kΩ)
1
0
MINIMUM WAKE-UP TIME (μs)
2.5
5.0
10
10 100
10968 G14
7.5
T
A
= 25°C
V
REF
= 5V
+
–
V
IN
R
SOURCE
+
TEMPERATURE (°C)
–60
LEAKAGE CURRENT (nA)
10
100
1000
100
10968 G15
1
0.1
0.01
–20
20
60
140
–40 0
40
80 120
V
REF
= 5V
V
CC
= 5V
ON CHANNEL
OFF CHANNEL
TEMPERATURE (°C)
–60
MINIMUM CLOCK FREQUENCY (kHz)
120
160
200
100
10968 G16
60
40
0
–20
20
60
140
–40 0
40
80 120
V
REF
= 5V
V
CC
= 5V
180
140
100
80
20
FREQUENCY (kHz)
1
0
ENOBs
2
4
6
8
10
10 100
10968 G17
9
7
5
3
1
T
A
= 25°C
V
CC
= V
REF
= 5V
f
SMPL
= 31.25kHz
FREQUENCY (kHz)
0
–100
AMPLITUDE (dB)
–90
–70
–60
–50
0
–30
2
4
10968 G18
–80
–20
–10
–40
6
8
10 12
14 16
T
A
= 25°C
V
CC
= V
REF
= 5V
f
SMPL
= 31.25kHz
f
IN
= 5.8kHz
LTC1096/LTC1096L
LTC1098/LTC1098L
11
10968fc
PIN FUNCTIONS
LTC1096/LTC1096L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1096/LTC1096L. A logic high on this
input disables the LTC1096/LTC1096L and disconnects the
power to the LTC1096/LTC1096L.
IN
+
(Pin 2): Analog Input. This input must be free of noise
with respect to GND.
IN
–
(Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
V
REF
(Pin 5): Reference Input. The reference input defi nes
the span of the A/D converter and must be kept free of
noise with respect to GND.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
V
CC
(Pin 8): Power Supply Voltage. This pin provides power
to the A/D converter. It must be free of noise and ripple by
bypassing directly to the analog ground plane.
LTC1098/LTC1098L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1098/LTC1098L. A logic high on this
input disables the LTC1098/LTC1098L and disconnects the
power to the LTC1098/LTC1098L.
CH0 (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
CH1 (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
D
IN
(Pin 5): Digital Data Input. The multiplexer address
is shifted into this pin.
D
OUT
(Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the se-
rial data transfer.
V
CC
(V
REF
)(Pin 8): Power Supply Voltage. This pin provides
power and defi nes the span of the A/D converter. It must
be free of noise and ripple by bypassing directly to the
analog ground plane.
LTC1096/LTC1096L
LTC1098/LTC1098L
12
10968fc
BLOCK DIAGRAM
LTC1096/LTC1096L
–
+
C
SAMPLE
BIAS AND
SHUTDOWN CIRCUIT
SERIAL PORT
V
CC
(V
CC
/V
REF
) CS CLK
D
OUT
IN
+
(CH0)
IN
–
(CH1)
MICROPOWER
COMPARATOR
CAPACITIVE DAC
SAR
V
REF
GND PIN NAMES IN PARENTHESES
REFER TO THE LTC1098/LTC1098L
(D
IN
)
10968 BD
TEST CIRCUITS
On and Off Channel Leakage Current Load Circuit for t
dDO
, t
r
and t
f
D
OUT
1.4V
3kΩ
100pF
TEST POINT
10968 TC02
5V
A
A
I
OFF
I
ON
POLARITY
OFF
CHANNEL
ON CHANNEL
10968 TC01
•
•
•
•
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

LTC1098LCS8#PBF

Mfr. #:
Buy LTC1098LCS8#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Analog to Digital Converters - ADC 8-bit 16.5ksps Micropower SAR ADC
Lifecycle:
New from this manufacturer.
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