LTC1096/LTC1096L
LTC1098/LTC1098L
15
10968fc
CS
10968 AI Ex
CLK
NULL BIT
B7
t
WAKEUP
10μs
t
su
t
su
t
WAKEUP
D
OUT
CS
CLK
D
OUT
APPLICATIONS INFORMATION
OVERVIEW
The LTC1096/LTC1096L/LTC1098/LTC1098L are 8-bit
micropower, switched-capacitor A/D converters. These
sampling ADCs typically draw 120μA of supply current
when sampling up to 33kHz. Supply current drops linearly
as the sample rate is reduced (see Supply Current vs
Sample Rate on the fi rst page of this data sheet). The ADCs
automatically power down when not performing conver-
sion, drawing only leakage current. They are packaged in
8-pin SO packages. The LTC1096L/LTC1098L operate on
a single supply ranging from 2.65V to 4V. The LTC1096
operates on a single supply ranging from 3V to 9V while
the LTC1098 operates from 3V to 6V supplies.
The LTC1096/LTC1096L/LTC1098/LTC1098L comprise an
8-bit, switched-capacitor ADC, a sample-and-hold and a
serial port (see Block Diagram). Although they share the
same basic design, the LTC1096(L) and LTC1098(L) differ
in some respects. The LTC1096(L) has a differential input
and has an external reference input pin. It can measure
signals fl oating on a DC common mode voltage and can
operate with reduced spans down to 250mV. Reducing the
span allows it to achieve 1mV resolution. The LTC1098(L)
has a 2-channel input multiplexer and can convert either
channel with respect to ground or the difference between
the two.
SERIAL INTERFACE
The LTC1098(L) communicates with microprocessors and
other external circuitry via a synchronous, half duplex,
4-wire serial interface while the LTC1096(L) uses a 3-wire
interface (see Operating Sequence in Figures 1 and 2).
Power Down and Wake-Up Time
The LTC1096(L)/LTC1098(L) draw power when the CS
pin is low and shut themselves down when that pin is
high. In order to have a correct conversion result, a 10μs
wake-up time must be provided from CS falling to the
fi rst falling clock (CLK) after the fi rst rising CLK for the
LTC1096(L) and from CS falling to the MSBF bit CLK fall-
ing for the LTC1098(L) (see Operating Sequence). If the
LTC1096(L)/LTC1098(L) are running with clock frequency
less than or equal to 100kHz, the wake-up time is inher-
ently provided.
Example
Two cases are shown at right to illustrate the relationship
among wake-up time, setup time and CLK frequency for
the LT1096(L).
In Case 1 the clock frequency is 100kHz. One clock cycle
is 10μs which can be the wake-up time, while half of that
can be the setup time. In Case 2 the clock frequency is
50kHz, half of the clock cycle plus the setup time (=1μs)
can be the wake-up time. If the CLK frequency is higher
than 100kHz, Figure 1 shows the relationship between the
wake-up time and setup time.
Case 2. Timing Diagram
Case 1. Timing Diagram
