LTC4302-1/LTC4302-2
15
sn430212 430212fs
OPERATIO
U
pulls down the voltage on the 50pF side with a delay of
55ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows t
PHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent bus capacitance on both
sides of the part. Larger output capacitances translate to
longer delays (up to 150ns). Users must quantify the
difference in propagation times for a rising edge versus a
falling edge in their systems and adjust setup and hold
times accordingly.
General Purpose Input/Outputs (GPIOs)
The LTC4302-1 provides two general purpose input/out-
put pins (GPIOs) that can be configured as inputs, open-
drain outputs or push-pull outputs. In push-pull mode, at
V
CC
= 2.7V, the typical pull-up impedance is 670Ω and the
typical pull-down impedance is 35Ω, making the GPIO
pull-downs capable of driving LEDs. The user must take
care to minimize the power dissipation in the pulldown
device. LEDs should have series resistors added to limit
current and the voltage drop across the internal pulldown
if their forward drop is less than about V
CC
-0.7V. Pullup
resistors should be sized to allow the internal pulldowns to
pull the GPIO pins below 0.7V. In open-drain output mode,
the user provides the logic high by connecting a resistor
to an external supply voltage. The external supply voltage
can range from 2.2V to 5.5V independent of the V
CC
voltage.
The LTC4302-2 replaces one GPIO pin with a V
CC2
pin and
provides only one GPIO.
Rise Time Accelerators
Rise time accelerator circuits on all four SDA and SCL pins
allow the user to choose weaker DC pull-up currents on the
bus, reducing power consumption while still meeting
system rise time requirements. A master on the bus may
activate the accelerators on the backplane side, the card
side, neither or both, by writing the LTC4302’s registers as
described above. When activated, the accelerators switch
in 2mA of current at V
CC
= 2.7V and 9mA at V
CC
= 5.5V
during positive bus transitions to quickly slew the SDA and
SCL lines once their DC voltages exceed 0.6V and the initial
rise rate on the pin exceeds 0.8V/µs. Using a general rule
of 20pF of capacitance for every device on the bus (10pF
for the device and 10pF for interconnect), choose a pull-up
current so that the bus will rise on its own at a rate of at
least 0.8V/µs to guarantee activation of the accelerators.
For example, assume an SMBus system with V
CC
= 3.3V,
a 10k pull-up resistor and equivalent bus capacitor of
200pF. The rise time of an SMBus system is calculated
from (V
IL(MAX)
– 0.15V) to (V
IH(MIN)
+ 0.15V) or 0.65V to
2.25V. It takes an RC circuit 0.92 time constants to
traverse this voltage for a 3.3V supply; in this case, 0.92 •
(10k • 200pF) = 1.84µs. Thus, the system exceeds the
maximum allowed rise time of 1µs by 84%. However,
using the rise time accelerators, which are activated at a
DC threshold below 0.65V, the worst-case rise time is
(2.25V – 0.65V) •␣ 200pF/1mA = 320ns, which meets the
1µs rise time requirement.
CONN Register Reset
Grounding CONN resets the registers to their default state
as specified in Tables 2 and 3. In the default state, the
backplane side is disconnected from the card side, the rise
time accelerators are disabled and the GPIOs are set in
open-drain output mode with the N-Channel MOSFET
open-drain pulldown turned off. Connecting a weak resis-
tor from CONN to ground on the I/O card and using a
staggered connector with CONN connecting to the short-
est pin guarantee glitch-free live board insertion and
removal. When the CONN voltage is brought back to V
CC
the registers remain in the default state and can then be
read or written to.
