LTC4302-1/LTC4302-2
8
sn430212 430212fs
OPERATIO
U
Live Insertion and Start-Up
The LTC4302 allows I/O card insertion into a live back-
plane without corruption of the data and clock busses
(SDA and SCL). In its main application, the LTC4302
resides on the edge of a peripheral card with the SCLOUT
pin connected to the card’s SCL bus and the SDAOUT
connected to the card’s SDA bus. If a card is plugged into
a live backplane via a staggered connector, ground and
V
CC
make connection first. The LTC4302 starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA and SCL pins until V
CC
rises above 2.5V
(typical). This ensures that the LTC4302 does not try to
function until it has sufficient bias voltage.
During this time, the 1V precharge circuitry is also active
and forces 1V through 100k nominal resistors to the SDA
and SCL pins. The concept of initializing the SDA and SCL
pins before they make contact with a live backplane is
described in the CompactPCI
TM
specification. Because the
I/O card is being plugged into a live backplane, the voltage
on the SDA and SCL busses may be anywhere between 0V
and V
CC
. Precharging the SCL and SDA pins to 1V mini-
mizes the worst-case voltage differential these pins will
see at the moment of connection, therefore minimizing the
amount of disturbance caused by the I/O card. The
LTC4302-1 precharges all four SDA and SCL pins when-
ever the V
CC
voltage is below its UVLO threshold voltage.
The LTC4302-2 precharges SDAIN and SCLIN whenever
V
CC
is below its UVLO threshold and precharges SDAOUT
and SCLOUT whenever V
CC2
is below its UVLO threshold.
After ground and V
CC
connect, SDAIN and SCLIN make
connection with the backplane SDA and SCL lines. Once
the part comes out of UVLO, the precharge circuitry is shut
off. Finally, the CONN pin connects to the short CONN pin
on the backplane, the 2-wire bus digital interface circuitry
is activated and a master on the bus can write to or read
from the LTC4302.
General I
2
C Bus/SMBus Description
The LTC4302 is designed to be compatible with the I
2
C and
SMBus two wire bus systems. I
2
C Bus and SMBus are
reasonably similar examples of two wire, bidirectional,
serial communication busses; however, calling them two
wire is not strictly accurate, as there is an implied third
wire which is the ground line. Large ground drops or
spikes between the grounds of different parts on the bus
can interrupt or disrupt communications, as the signals on
the two wires are both inherently referenced to a ground
which is expected to be common to all parts on the bus.
Both bus types have one data line and one clock line which
are externally pulled to a high voltage when they are not
being controlled by a device on the bus. The devices on the
bus can only pull the data and clock lines low, which makes
it simple to detect if more than one device is trying to
control the bus; eventually, a device will release a line and
it will not pull high because another device is still holding
it low. Pullups for the data and clock lines are usually
provided by external discrete resistors, but external cur-
rent sources can also be used. Since there are no dedi-
cated lines to use to tell a given device if another device is
trying to communicate with it, each device must have a
unique address to which it will respond. The first part of
any communication is to send out an address on the bus
and wait to see if another device responds to it. After a
response is detected, meaningful data can be exchanged
between the parts.
Typically, one device controls the clock line at least most
of the time and normally sends data to the other parts and
polls them to send data back. This device is called the
master. There can be more than one master, since there is
an effective protocol to resolve bus contentions, and non-
master (slave) devices can also control the clock to delay
rising edges to give themselves more time to complete
calculations or communications (clock stretching). Slave
devices need to control the data line to acknowledge
communications from the master. Some devices need to
send data back to the master; they will be in control of the
data line while they are doing so. Many slave devices have
no need to stretch the clock signal, which is the case with
the LTC4302.
Data is exchanged in the form of bytes, which are 8-bit
packets. Any byte needs to be acknowledged by the slave
or master (data line pulled low) or not acknowledged by
the master (data line left high), so communications are
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers
Group.
