74ACTQ646SC Datasheet 74ACTQ646SC, 74ACTQ646SCX, 74ACQ646SC | P1-P3

January 1990

Revised September 2000

74ACQ646 • 74ACTQ646 Quiet Series



Octal Transceiver/Register with 3-STATE Outputs

74ACQ646 • 74ACTQ646

Quiet Series

 Octal Transceiver/Register

with 3-STATE Outputs

General Description

The ACQ/ACTQ646 consist of registered bus transceiver

circuits, with outputs, D-type flip-flops, and control circuitry

providing multiplexed transmission of data directly from the

input bus or from the internal storage registers. Data on the

A or B bus will be loaded into the respective registers on

the LOW-to-HIGH transition of the appropriate clock pin

(CPAB or CPBA). The four fundamental handling functions

available are illustrated in Figure 1, Figure 2, Figure 3 and

Figure 4.

The ACQ/ACTQ utilizes Fairchild Quiet Series

 technol-

ogy to guarantee quiet output switching and improved

dynamic threshold performance. FACT Quiet Series

 fea-

tures GTO

 output control and undershoot corrector in

addition to a split ground bus for superior performance.

Features

■ Guaranteed simultaneous switching noise level and

dynamic threshold performance

■ Guaranteed pin-to-pin skew AC performance

■ Independent registers for A and B busses

■ Multiplexed real-time and stored data transfers

■ 300 mil slim dual-in-line package

■ Outputs source/sink 24 mA

■ Faster prop delays than the standard AC/ACT646

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram Pin Descriptions

FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation

Order Number Package Number Package Description

74ACQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74ACQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

74ACTQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74ACTQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Descriptions

–A

Data Register A Inputs

Data Register A Outputs

–B

Data Register B Inputs

Data Register B Outputs

CPAB, CPBA Clock Pulse Inputs

SAB, SBA Transmit/Receive Inputs

Output Enable Input

DIR Direction Control Input

www.fairchildsemi.com 2

74ACQ646 • 74ACTQ646

Logic Symbols

IEEE/IEC

Function Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G

and DIR inputs. Data input functions are always enabled; i.e., data

at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

Inputs Data I/O (Note 1)

Function

DIR CPAB CPBA SAB SBA A

–A

–B

H X H or L H or L X X Isolation

X X X Input Input Clock A

Data into A Register

HXX

X X Clock B

Data into B Register

LHXXLX A

to B

—Real Time (Transparent Mode)

X L X Input Output Clock A

Data into A Register

L H H or L X H X A Register to B

(Stored Mode)

X H X Clock A

Data into A Register and Output to B

LLXXXL B

to A

—Real Time (Transparent Mode)

LLX

X L Output Input Clock B

Data into B Register

L L X H or L X H B Register to A

(Stored Mode)

LLX

X H Clock B

Data into B Register and Output to A

3 www.fairchildsemi.com

74ACQ646 • 74ACTQ646

Real Time Transfer

A-Bus to B-Bus

FIGURE 1.

Real Time Transfer

B-Bus to A-Bus

FIGURE 2.

Storage from

Bus to Register

FIGURE 3.

Transfer from

FIGURE 4.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

P1-P3 P4-P6 P7-P9 P10-P10

74ACTQ646SC

Mfr. #:

Buy 74ACTQ646SC

Manufacturer:

ON Semiconductor / Fairchild

Description:

Bus Transceivers Octal Trans/Reg

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

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74ACTQ646SC

74ACTQ646SC

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