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74ACQ646 74ACTQ646
AC Electrical Characteristics for ACTQ
Note 17: Voltage Range 5.0 is 5.0V ± 0.5V
Note 18: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for ACTQ
Note 19: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
V
CC
T
A
= +25°CT
A
= 40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF C
L
= 50 pF
Units
(Note 17) Min Typ Max Min Max
t
PLH
Propagation Delay
5.0 2.5 8.5 10.5 2.5 11.0 ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
5.0 2.0 8.0 10.0 2.0 10.5 ns
t
PHL
Bus to Bus
t
PLH
Propagation Delay
t
PHL
SBA or SAB to A
n
or B
n
5.0 2.5 8.5 10.5 2.5 11.0 ns
(w/A
n
or B
n
HIGH or LOW)
t
PZH
Enable Time
5.0 2.5 10.0 12.0 2.5 12.5 ns
t
PZL
G to A
n
or B
n
t
PHZ
Disable Time
5.01.07.08.51.09.0ns
t
PLZ
G to A
n
or B
n
t
PZH
Enable Time
5.0 2.5 10.0 12.0 2.5 12.5 ns
t
PZL
DIR to A
n
or B
n
t
PHZ
Disable Time
5.01.07.08.51.09.0ns
t
PLZ
DIR to A
n
or B
n
t
OSHL
Output to Output
t
OSLH
Skew (Note 18) Select to Bus 5.0 0.5 1.0 1.0 ns
or Clock to Bus
t
OSHL
Output to Output
t
OSLH
Skew (Note 18) 5.0 1.0 1.5 1.5 ns
Bus to Bus
V
CC
T
A
= +25°CT
A
= 40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF C
L
= 50 pF
Units
(Note 19) Typ Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0 3.0 3.0 ns
Bus to Clock
t
H
Hold Time, HIGH or LOW
5.0 1.5 1.5 ns
Bus to Clock
t
W
Clock Pulse Width
5.0 4.0 4.0 ns
HIGH or LOW
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
= OPEN
C
I/O
Input/Output Capacitance 15.0 pF V
CC
= 5.0V
C
PD
Power Dissipation Capacitance 90.0 pF V
CC
= 5.0V
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74ACQ646 74ACTQ646
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 5. Quiet Output Noise Voltage Waveforms
Note 20: V
OHV
and V
OLP
are measured with respect to ground reference.
Note 21: Input pulses have the following characteristics: f = 1MHz,
t
r
= 3ns, t
f
= 3 ns, skew < 150 ps.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, V
IL
,until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 6. Simultaneous Switching Test Circuit
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74ACQ646 74ACTQ646
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B

74ACTQ646SC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers Octal Trans/Reg
Lifecycle:
New from this manufacturer.
Delivery:
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