©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC02, 74ACT02 Rev. 1.5.1 9
74AC02, 74ACT02 — Quad 2-Input NOR Gate
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
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14 8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A)
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30
5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35
2.54
3.81
3.17
8.82
(1.74)
