WM8521 Production Data
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PD, Rev 4.2, February 2013
10
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio systems
Master Clock. The external master clock can be applied directly through the MCLK input pin with no
configuration necessary for sample rate selection.
Note that on the WM8521, MCLK is used to derive clocks for the DAC path. The DAC path is affected
by DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system
where there are a number of possible sources for the reference clock it is recommended that the
clock source with the lowest jitter be used to optimise the performance of the DAC.
The device can be reset by stopping MCLK. In this state the power consumption is substantially
reduced.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Three interface
formats are supported:
I
2
S mode
Right Justified mode
DSP mode
All formats send the MSB first. The data format is selected with the FORMAT pin. When FORMAT is
LOW, right justified data format is selected and word lengths up to 16-bits may be used. If a word
length shorter than 16-bits is used, the unused bits should be padded with zeroes. When the
FORMAT pin is HIGH, I
2
S format is selected and word length of any value up to 32-bits may be used.
Unless in 16-bit packed mode, if a word length shorter than 24-bits is used, the unused bits should
be padded with zeros. If LRCLK is 4 BCLKs or less duration, the 16bit DSP compatible format is
selected. Mode A and B clock formats are supported, selected by the state of the FORMAT pin.
I
2
S MODE INPUT FORMAT
The WM8521 supports word lengths of 16-32 bits in I
2
S mode.
In I
2
S mode, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed
with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing
reference to indicate the beginning or end of the data words.
25-32 bits: LRCLK must be high for a minimum of data wordlength BCLKs and low for a minimum of
data wordlength BCLKs. The LSBs will be truncated and the most significant 24 bits will be used by
the internal processing.
24 bits: LRCLK must be high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
17-23 bits: Data must be zero padded to 24 bits and LRCLK must be high for a minimum of 24 BCLKs
and low for a minimum of 24 BCLKs.
Up to 16 bits: EITHER data must be zero padded to 24 bits and LRCLK must be high for minimum 24
BCLKs and low for 24 BCLKs,
OR data must be zero padded to 16 bits and LRCLK must be high for exactly 16 BCLKs and low for
exactly 16 BCLKs. The device auto-detects this 16-bit packed mode and switches to 16-bit data
length.
Any mark to space ratio on LRCLK is acceptable provided the above requirements are met.
